DLL Clock Control for Stable Power-Down Self-Refresh
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Solution Overview
Problem
Conventional semiconductor apparatuses experience increased likelihood of misoperation due to repeated activation and deactivation of DLL clock generation and output enable signal generation units during frequent power-down and self-refresh modes, particularly as the delay time of the delay line increases.
Innovation Solution
Incorporating a delay detection unit to generate a delay detection signal based on the delay time of the delay line, which activates or deactivates the DLL clock generation unit and prevents resetting during power-down mode, and controls the buffer enable signal to maintain stable operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the DLL clock generation unit is deactivated during power-down mode, then power consumption is reduced, but misoperation occurs due to repeated activation and deactivation
Solution Approach 1:
The patent implements dynamic control of the DLL clock generation unit based on delay time conditions. The unit is selectively deactivated only when delay time is below a threshold, while maintaining activation when delay time exceeds the threshold. This dynamic behavior optimizes power consumption without causing misoperation, resolving the contradiction between energy efficiency and operational reliability.
Solution Approach 2:
The patent changes the operational state of the DLL clock generation unit based on the parameter of delay time. By monitoring whether delay time meets a predetermined condition, the system dynamically adjusts activation/deactivation decisions, thereby reducing power consumption while preventing misoperation that would occur with frequent state changes.
2Adaptability or versatility
If the delay time of the delay line is increased, then clock phase adjustment range is improved, but the likelihood of misoperation increases during power-down mode
Solution Approach 1:
The patent implements a feedback mechanism where the delay time is monitored and used to control the activation state of the DLL clock generation unit. When delay time exceeds a predetermined threshold, the unit remains active; when it falls below, the unit is deactivated. This feedback-based control prevents misoperation while maintaining the ability to achieve required clock phase adjustments.
Solution Approach 2:
The patent uses delay time as a control parameter to dynamically change the operational state of the DLL clock generation unit. By setting a threshold for delay time, the system ensures that the unit operates only under conditions where it can function reliably, thus preventing misoperation while maintaining adequate clock phase adjustment capability.
3Productivity
If the DLL clock generation unit is repeatedly activated and deactivated during frequent power-down modes, then power management is improved, but misoperation likelihood increases
Solution Approach 1:
The patent implements dynamic state management where the DLL clock generation unit's activation state is determined by real-time delay time conditions. This prevents unnecessary activation/deactivation cycles that would occur with fixed power management policies, thereby improving power management efficiency while maintaining operational stability.
Solution Approach 2:
The patent changes the operational policy based on the delay time parameter. Instead of uniformly deactivating the DLL clock generation unit during all power-down modes, the system selectively maintains activation when delay time conditions are favorable, reducing unnecessary state transitions and improving both power management and reliability.
Data Source
AI summary
A semiconductor apparatus includes a DLL clock generation unit configured to compare phases of a clock and a feedback clock, determine a delay time of a delay line, delay the clock by the delay time through the delay line, and generate a DLL clock; a delay detection unit configured to detect the delay time of the delay line and enable a delay detection signal when the delay time is greater than or equal to a predetermined time; and a power-down control unit configured to prevent the DLL clock generation unit from being reset when the delay detection signal is enabled and reset the DLL clock generation unit when the delay detection signal is disabled, in a self-refresh operation under a power-down mode.