Delay Locked Loop Clock Pulse Shaping for Skewed Memory Lines
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Solution Overview
Problem
Semiconductor memory apparatuses experience timing errors due to skews in delay locked loop clocks RCLKDLL and FCLKDLL caused by asymmetrical signal lines, leading to data input/output errors, especially in high-speed operations where overlapping clock intervals result in excessive errors.
Innovation Solution
A delay locked loop circuit that includes a duty cycle correcting part, a clock pulse width detecting part, and a pulse width adjusting part to adjust the pulse widths of phase-divided signals RCLKDLL and FCLKDLL, ensuring they do not overlap, even when transmitted through asymmetrical signal lines, by detecting the external clock's pulse width and adjusting the pulse widths accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If delay locked loop clocks are transmitted through asymmetrical signal lines, then the semiconductor memory apparatus can operate at high speed with increased data load, but timing errors occur due to clock skews causing overlapping clock intervals
Solution Approach 1:
The patent adjusts the pulse width parameter of the delay locked loop clocks to prevent overlapping. By dynamically changing the pulse width based on the external clock frequency and transmission characteristics, the system maintains reliable operation while supporting high-speed data input/output through asymmetrical signal lines
2Reliability
If the pulse width of delay locked loop clocks is increased to prevent overlapping, then timing errors are reduced, but the flexibility to adapt to different external clock frequencies is reduced
Solution Approach 1:
The patent implements dynamic pulse width adjustment that adapts to different external clock frequencies. The pulse width is not fixed but is dynamically controlled based on the operating conditions and clock frequency, allowing the system to maintain timing accuracy across a range of frequencies while preserving adaptability
3Manufacturing precision
If duty cycle correction is applied to the delay locked loop clocks, then the pulse widths become more consistent, but additional circuit complexity is introduced
Solution Approach 1:
The patent combines the duty cycle correction function with the existing delay locked loop circuitry. By integrating the pulse width adjustment mechanism into the clock generation path rather than adding completely separate correction circuits, the system achieves consistent pulse widths while minimizing additional circuit complexity
Data Source
AI summary
A delay locked loop circuit for a semiconductor memory apparatus includes a duty cycle correcting part that corrects and outputs duty cycles of internal clocks. A clock pulse width detecting part detects a pulse width of an external clock and outputs a pulse width detecting signal. A driving part divides a phase of the output of the duty cycle correcting part, adjusts a pulse width of at least one of two signals, which are obtained by dividing the phase, in accordance with the pulse width detecting signal, and outputs the two signals as delay locked loop clocks.