DLL Clock Recovery for Low-Power Wireless Communication
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Solution Overview
Problem
In low-power wireless communication devices, frequency synthesizers such as phase-locked loops (PLL) and voltage-controlled oscillators (VCO) consume a significant portion of the overall power, leading to high power consumption and potential noise issues when turned on and off.
Innovation Solution
A wireless communication device that recovers a clock frequency using a delay-locked loop (DLL) to generate a delayed signal, which is combined with the input signal to produce a clock signal without the need for a PLL, thereby reducing power consumption by dynamically adjusting the delay time based on the difference between the input and delayed signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency synthesizer (PLL or VCO) is used for clock recovery, then reliable clock frequency recovery is achieved, but power consumption increases significantly
Solution Approach 1:
The patent extracts the essential function of clock recovery from the complex PLL/VCO system and implements it using a simplified delay-locked loop (DLL) that operates directly on the received signal's carrier frequency, eliminating the need for frequency synthesis while maintaining recovery reliability
Solution Approach 2:
The patent creates a delayed copy of the received signal and uses correlation between the original and delayed versions to detect carrier-off intervals, providing a low-power alternative to active frequency synthesis while preserving clock recovery functionality
2Use of energy by moving object
If PLL and VCO are dynamically turned on and off to reduce power consumption, then energy savings are achieved, but noise issues and reliability problems occur
Solution Approach 1:
The patent employs periodic sampling of the received signal at the carrier frequency, using delayed versions of the signal to detect carrier-off intervals rhythmically, which avoids the noise and reliability issues associated with dynamically switching PLL/VCO components on and off
Solution Approach 2:
The system uses the received signal itself to generate the clock frequency through delay-based correlation, eliminating the need for separate frequency synthesizer components that would require dynamic power management and generate noise when switched
3Measurement precision
If delay time is increased to improve carrier-off interval detection, then detection accuracy improves, but signal distortion and timing errors increase
Solution Approach 1:
The patent dynamically adjusts the delay time based on the symbol period of the received signal, optimizing the delay to be approximately half the symbol period for binary FSK signals, which maximizes detection accuracy while maintaining signal integrity through adaptive timing
Solution Approach 2:
The system changes the delay parameter adaptively based on signal characteristics, using different delay values for different modulation schemes (e.g., half symbol period for binary FSK) to optimize both detection precision and signal reliability
Data Source
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AI summary
A device with wireless communication includes: an input receiver configured to receive an input signal having a carrier frequency; a delay circuit configured to generate a delayed signal by delaying the input signal; and a clock generator configured to generate a clock signal having a clock frequency based on the delayed signal and the input signal.