Delay Locked Loop Clock Segmentation for High-Speed Memory Output
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Solution Overview
Problem
Conventional delay locked loops in semiconductor memory devices face limitations in operation frequency due to a narrow permissible range of delay for generating data output enable signals, leading to potential malfunctions as the frequency increases.
Innovation Solution
The proposed solution involves a delay locked loop with a first driving block generating DLL clocks for read operations and a second driving block with a smaller delay amount for write operations, ensuring a sufficient operation margin by differing delay amounts between the two blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single delay amount is used for both read and write operations in conventional DLLs, then the circuit complexity is reduced, but the operation frequency is limited due to narrow permissible delay range for generating data output enable signals
Solution Approach 1:
The DLL is segmented into two independent driving blocks: a first driving block with a first delay amount for read operations, and a second driving block with a second delay amount for write operations. This segmentation allows each block to be optimized independently for its specific operation type, enabling higher operation frequencies while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
Different delay characteristics are applied to different functional blocks within the DLL. The first driving block uses a first delay amount optimized for read operations, while the second driving block uses a second delay amount optimized for write operations. This local differentiation of delay properties allows each block to operate at optimal frequencies for its specific function, resolving the contradiction between overall frequency improvement and circuit complexity.
2Reliability
If the delay amount is increased to provide sufficient operation margin for data output enable signals, then reliability improves, but the operation frequency decreases
Solution Approach 1:
The DLL employs dynamic delay adjustment through two independent delay control mechanisms: a first delay controller for the first driving block and a second delay controller for the second driving block. This dynamic control allows the delay amounts to be precisely tuned to provide sufficient operation margin for reliability while maintaining high operation frequencies, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent changes the delay parameter differently for different operational modes by implementing a first delay amount for read operations and a second delay amount for write operations. This parameter differentiation allows optimization of operation margin for reliability in each mode while maintaining high frequency operation, effectively resolving the contradiction between reliability and productivity.
Data Source
AI summary
A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.