Delay-Locked Loop Clock Selection for Smaller Delay-Line Area
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in synchronous DRAMs require two separate delay lines, increasing design area without achieving equivalent performance.
Innovation Solution
A DLL configuration that uses a clock selector to choose between normal-phase and reverse-phase external clocks, with a first delay line and an inverted second delay line, allowing for reduced delay amounts and design area while maintaining performance by using half the delay of conventional DLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate delay lines are used in conventional DLLs, then the delay locking function is achieved, but the design area increases
Solution Approach 1:
The patent merges the functionality of two separate delay lines into a single delay line by using a clock selector to choose between normal-phase and reverse-phase external clocks. This combining approach maintains the delay locking function while reducing the design area, as the single delay line processes whichever clock phase is needed based on the selection signal from the phase detector.
Solution Approach 2:
The single delay line in the patent serves multiple functions by processing different clock phases (normal-phase or reverse-phase) selected by the clock selector. This multi-functional approach allows the same delay line to replace what would traditionally require two separate delay lines, thereby reducing design area while maintaining full delay locking capability.
2Area of stationary object
If delay amount is reduced by half, then design area is reduced, but delay precision must be maintained
Solution Approach 1:
The patent changes the operating parameters by using both normal-phase and reverse-phase external clocks with a single delay line. This parameter change allows the delay line to achieve the necessary phase alignment with half the delay amount, reducing design area while maintaining precision through the alternating use of different clock phases and the phase mixer's intermediate phase generation.
Data Source
AI summary
A delay locked loop is disclosed which includes a clock selector for selecting and outputting any one of normal-phase and reverse-phase external clocks in response to a clock selection information signal, a first delay line for delaying an output signal from the clock selector by a predetermined amount of time, a second delay line for delaying an inverted version of an output signal from the first delay line by a predetermined amount of time, and a phase mixer for mixing a phase of the output signal from the first delay line and a phase of an output signal from the second delay line and outputting an internal clock having a corrected duty cycle as a result of the mixing.