Delay Locked Loop Clock Testing with Multiphase Signal Merging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Accurate measurement of time delays in delay locked loops is challenging due to environmental influences and the increased frequency of clocks, leading to measurement errors and increased power supply and ground jitter, complicating the testing process.
Innovation Solution
A delay locked loop detection system that includes a pre-receiving circuit for amplifying and shaping the reference clock and a multiphase multiplexing circuit for synthesizing multiple clock signals with different delays into a single signal, reducing the need for multiple clock measurements and lowering environmental and instrument requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delayed clocks are measured one-by-one, then measurement coverage is complete, but consumption of driving circuit increases and jitters of power supply and ground increase
Solution Approach 1:
The patent combines multiple delayed clock signals into a single composite signal for measurement. The measurement device measures the time delay of the composite signal containing multiple delayed clocks simultaneously, eliminating the need for separate measurements of each clock signal, thereby reducing power supply and ground jitter while maintaining complete measurement coverage.
2Ease of operation
If reference clock is directly input into DLL, then testing process is simple, but reference clock attenuates and distorts due to testing environment
Solution Approach 1:
The patent introduces a pre-receiving circuit as an intermediary between the reference clock source and the delay locked loop. This circuit amplifies and shapes the reference clock signal before it enters the DLL, compensating for signal attenuation and distortion caused by the testing environment, thereby maintaining signal quality without complicating the overall testing process.
3Measurement precision
If multiple delayed clocks are measured separately, then measurement accuracy of individual clocks is maintained, but testing progress becomes complicated and difficult
Solution Approach 1:
The patent merges multiple delayed clock signals into a single composite signal that contains information about all delayed clocks. The measurement device then measures the time delay of this composite signal, which provides measurement coverage for all individual clocks simultaneously, thereby simplifying the testing process while maintaining measurement accuracy through the composite signal analysis.
4Speed
If clock frequency increases continuously, then clock performance improves, but environmental influence becomes more non-neglected and measurement accuracy decreases
Solution Approach 1:
The pre-receiving circuit acts as an intermediary that conditions the high-frequency reference clock signal before it enters the delay locked loop. By amplifying and shaping the signal at this early stage, the circuit ensures that even at increased frequencies where environmental influences are more significant, the signal quality remains sufficient for accurate time delay measurements.
Data Source
AI summary
A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing instrument (500). Also included is a delay locked loop detection method. The system and method mentioned above enable an accurate measurement for the delays of the delay locked loop.