DLL Clock Modulation for Memory Data Strobe EMI Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data input/output speed synchronization with increasing data processor speeds, leading to degraded Electromagnetic Interference (EMI) characteristics due to fixed clock frequencies, especially when the Spread Spectrum Clock (SSC) function is not operated correctly.
Innovation Solution
Incorporating a Delay Locked Loop (DLL) circuit with a modulation controller to generate frequency-modulated clocks, which corrects the duty ratio and outputs these as data strobe signals, thereby improving EMI characteristics by varying the clock frequency within a predetermined range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed frequency clock is used for data transfer, then data synchronization is achieved, but EMI characteristics are degraded due to power spectrum concentration
Solution Approach 1:
The patent applies dynamics by transforming the fixed frequency clock into a frequency-modulated clock. The DLL circuit dynamically adjusts the clock frequency around a center frequency, creating a time-varying frequency signal that spreads the power spectrum. This dynamic frequency modulation maintains data synchronization while preventing EMI degradation caused by single-frequency concentration.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal from a fixed value to a modulated value. The frequency-modulated clock varies its frequency within a predetermined range centered around a center frequency, which spreads the power spectrum across multiple frequencies. This parameter change resolves the contradiction by maintaining synchronization through the center frequency while distributing energy across the spectrum to improve EMI characteristics.
2Productivity
If the SSC function is not operated correctly, then data transfer speed is maintained, but EMI characteristics are degraded due to single peak power spectrum
Solution Approach 1:
The patent implements feedback through the DLL circuit, which continuously monitors and adjusts the clock frequency. The DLL uses phase detection and feedback control to maintain the frequency-modulated clock at the correct center frequency while allowing frequency modulation. This feedback mechanism ensures that data transfer speed is maintained through proper synchronization while the frequency modulation spreads the power spectrum to improve EMI characteristics.
3Reliability
If a delay locked loop is used to compensate clock delay, then data synchronization is improved, but the clock frequency remains fixed causing EMI issues
Solution Approach 1:
The patent merges the DLL delay locking function with frequency modulation capability. The DLL circuit not only compensates for clock delay to achieve data synchronization but also generates a frequency-modulated clock output. This combination of delay locking and frequency modulation in a single circuit resolves the contradiction by simultaneously achieving synchronization and improving EMI characteristics through spectrum spreading.
Data Source
AI summary
A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal.