Delay-Locked Loop Clock Switching for Low-Power Memory Output
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Solution Overview
Problem
High-frequency clock signals in semiconductor memory devices increase power consumption, making it difficult to realize low-power consuming devices with efficient clock signal synchronization.
Innovation Solution
A delay-locked loop circuit that selects between a divided clock signal and a reference clock signal based on a determined mode, using a first and second delay-locked-mode-based selector, and a delay-locked mode controller to control the selectors and active/inactive states of data signal generators, thereby generating a delay-locked clock signal with reduced power consumption and locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency clock signals are used to perform operations at higher speeds, then operational speed is improved, but power consumption increases
Solution Approach 1:
The delay-locked loop circuit dynamically switches between two operational modes: a first mode using a divided clock signal (lower frequency) for normal operations, and a second mode using a reference clock signal (higher frequency) when data output operations are required. This dynamic mode switching allows the system to adapt its clock frequency to operational needs, achieving high speed only when necessary while consuming less power during normal operations.
Solution Approach 2:
The invention changes the clock signal frequency parameter based on operational requirements. By using a divided clock signal (lower frequency) during normal operations and switching to a reference clock signal (higher frequency) during data output operations, the system optimizes the balance between speed and power consumption by adjusting the frequency parameter dynamically.
2Reliability
If a delay-locked loop circuit is used to compensate for clock skew and synchronize internal clock signal phase with external clock signal, then clock synchronization is improved, but power consumption increases
Solution Approach 1:
The delay-locked loop circuit operates dynamically by switching between a first delay-locked mode (using divided clock signal) and a second delay-locked mode (using reference clock signal). This dynamic operation allows the circuit to maintain clock synchronization functionality while reducing power consumption by using the lower-frequency divided clock signal during normal operations.
Solution Approach 2:
The circuit employs periodic mode switching based on operational requirements. During normal operations, it uses the first delay-locked mode with divided clock signal for reduced power consumption. When data output operations are detected, it switches to the second delay-locked mode with reference clock signal to ensure proper synchronization, then returns to the first mode afterward.
3Measurement precision
If the reference clock signal is used to generate internal clock signal with same phase as external clock signal, then clock phase accuracy is improved, but power consumption increases
Solution Approach 1:
The invention changes the clock signal parameter (frequency and source) based on operational requirements. By using a divided clock signal during normal operations and switching to a reference clock signal during data output operations, the system achieves high phase accuracy only when necessary, thereby optimizing power consumption while maintaining clock synchronization quality.
4Speed
If high-frequency clock signals are used for data output operations, then data output speed is improved, but locking time increases
Solution Approach 1:
The delay-locked loop circuit maintains readiness by pre-configuring the mode switching mechanism. When a data output operation is detected, the circuit can quickly switch to the second delay-locked mode using the reference clock signal, avoiding the need for lengthy locking procedures. The preliminary setup of the mode switching infrastructure enables rapid transition to high-speed operation when needed.
Data Source
AI summary
Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.