Delay-Locked Loop Clock Switching for Low-Power Memory Timing
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Solution Overview
Problem
High-frequency clock signals in semiconductor memory devices increase power consumption, making it difficult to realize low-power consuming devices with efficient clock synchronization.
Innovation Solution
A delay-locked loop circuit that selects between a divided clock signal and a reference clock signal based on a received command, using a first and second delay-locked-mode-based selector, and a delay-locked mode controller to determine the mode for generating a delay-locked clock signal, thereby reducing power consumption and locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency clock signals are used to perform operations at higher speeds, then operational speed is improved, but power consumption increases
Solution Approach 1:
The delay-locked loop circuit dynamically switches between two operating modes: a first mode using a divided clock signal for normal operations, and a second mode using a reference clock signal for data output operations. This dynamic adaptation allows the system to optimize between power consumption and operational speed based on real-time requirements.
Solution Approach 2:
The system changes the frequency parameter of the clock signal based on operational needs. During normal operations, a divided clock signal with lower frequency is used to reduce power consumption. When data output operations are required, the system switches to a reference clock signal with higher frequency to ensure timely data output, thus changing the clock frequency parameter adaptively.
2Reliability
If a reference clock signal is used to generate an internal clock signal with the same phase, then clock synchronization is improved, but power consumption increases
Solution Approach 1:
The delay-locked loop circuit dynamically selects between using a divided clock signal or a reference clock signal based on the operational state. During normal operations, the divided clock signal is used to reduce power consumption while maintaining adequate synchronization. When data output operations are detected, the system dynamically switches to using the reference clock signal to ensure precise clock synchronization and timely data output.
3Reliability
If clock skew compensation is performed using a delay-locked loop circuit, then timing synchronization is improved, but locking time increases
Solution Approach 1:
The system performs preliminary actions by pre-configuring the delay-locked loop circuit with appropriate delay settings based on the operational mode. When a data output operation is detected, the system has already prepared the reference clock signal path, allowing for faster locking without requiring extensive delay adjustments during the critical data output period.
Data Source
AI summary
Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.