Delay-Locked Loop Clock Switching for Stable Power-Down Phase Lock
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Solution Overview
Problem
The existing DLL circuits in semiconductor memory devices face locking failures due to changes in circumstances such as external temperature during extended power down modes, leading to inaccurate data transmission and reception.
Innovation Solution
A DLL circuit with a power down mode controller, first and second clock buffers, a clock selection unit, and a phase update unit that performs phase updates using different frequency internal clock signals in normal and power down modes, ensuring stable operation by performing at least one phase update operation during power down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL circuit enters power down mode to save power, then power consumption is reduced, but phase synchronization accuracy deteriorates due to temperature changes during extended power down periods
Solution Approach 1:
The patent performs a phase update operation during the power down mode using a second clock signal before the DLL circuit exits power down mode. This preliminary action compensates for phase shifts that occur during temperature changes in power down mode, ensuring that the phase synchronization accuracy is maintained when the circuit returns to normal operation, thus resolving the contradiction between power savings and synchronization accuracy.
2Loss of energy
If the clock buffer is turned off during power down mode to save current, then power consumption is reduced, but the DLL circuit cannot maintain accurate phase locking due to circumstance changes
Solution Approach 1:
The patent performs a phase update operation during power down mode using a second clock signal that is generated even when the clock buffer is turned off. This preliminary phase update compensates for temperature-induced phase shifts that occur during power down, ensuring accurate phase locking is restored when the clock buffer is turned back on, thus resolving the contradiction between current savings and phase locking accuracy.
3Reliability
If the DLL circuit performs continuous phase updates in normal mode, then phase synchronization is maintained, but power consumption increases during idle periods
Solution Approach 1:
The patent implements periodic phase update operations during power down mode using a second clock signal at a lower frequency. This periodic action maintains phase synchronization stability during idle periods when the DLL is in power down mode, while consuming significantly less power compared to continuous phase updates in normal mode, thus resolving the contradiction between synchronization stability and power consumption during idle periods.
Data Source
AI summary
A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock buffering unit buffers an external clock signal in response to the power down mode control signal and outputs first and second internal clock signals. A clock selection unit selects one of the first and second internal clock signals based on the power down mode control signal to output the selected signal as an intermediate output clock signal. A phase update unit performs a phase update operation by using the intermediate output clock signal to output a delay locked loop (DLL) clock signal, the first internal clock signal differing in frequency from the second internal clock signal.