DLL Clock Trimming Circuit for Low-Jitter Delay Synchronization
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) in synchronous memory devices face challenges with noise-induced clock jitter and high power consumption due to the need for extensive delay stages and static delay circuits, which are susceptible to electrical noise and increase power consumption.
Innovation Solution
A clock signal generator circuit with a DLL and trimming circuit that uses first and second adjustable delays to trim unadjusted forward delays and duty cycles, minimizing forward delay paths and reducing susceptibility to noise-induced jitter while lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive delay stages and static delay circuits are used in conventional DLLs, then delay trimming capability is improved, but noise-induced clock jitter and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the static delay circuit from the conventional DLL structure. Instead of using extensive delay stages, the invention uses a minimal delay path combined with a separate trimming circuit that adjusts the phase of the feedback signal. This removes the source of noise-induced jitter while preserving delay trimming capability through the alternative trimming mechanism.
Solution Approach 2:
The patent segments the delay adjustment function into two separate components: a minimal fixed delay path and a variable trimming circuit. The trimming circuit independently adjusts the feedback signal phase without requiring extensive delay stages in the main signal path, thereby reducing noise susceptibility while maintaining trimming capability.
2Measurement precision
If extensive delay stages and static delay circuits are used in conventional DLLs, then delay trimming capability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming static delay circuit from the conventional DLL architecture. The trimming function is achieved through a more energy-efficient mechanism that adjusts the feedback signal phase without requiring continuous operation of extensive delay stages, thereby significantly reducing power consumption while maintaining trimming capability.
Solution Approach 2:
The patent transitions from a static delay circuit to a dynamic trimming approach where the trimming circuit actively adjusts the feedback signal phase based on detected timing differences. This dynamic adjustment requires less continuous power consumption compared to maintaining extensive static delay stages throughout the clock period.
3Adaptability or versatility
If forward delay paths are extended to accommodate trimming requirements, then delay adjustment range is improved, but susceptibility to noise-induced jitter increases
Solution Approach 1:
The patent introduces a trimming circuit as an intermediary that adjusts the feedback signal phase without requiring extended forward delay paths. This intermediary mechanism provides the necessary delay adjustment range while keeping the main signal path short and thus less susceptible to noise-induced jitter.
Solution Approach 2:
The patent moves the delay adjustment function from the time domain (extended delay paths) to the phase domain (feedback signal phase adjustment). By trimming the phase of the feedback signal rather than extending the forward delay path, the system achieves the required adjustment range with minimal exposure to noise in the critical signal path.
Data Source
AI summary
A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.