DLL Clock Window Control for Low-Power Memory Timing
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high data reliability, high-speed memory access, low power consumption, and reduced chip size, particularly due to the need for tightly controlling clock signal generation windows to minimize power usage.
Innovation Solution
The implementation of a delay-locked loop (DLL) circuitry that includes a delay line with adjustable delays to align the phase of internal clock signals with an external clock signal, and additional circuitry to measure the length of the delay path and tightly control the window during which the internal clock signal is generated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal generation window is extended to ensure reliable operation and accommodate delays, then the reliability and speed of memory access are improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic control of the clock signal generation window by using a delay-locked loop (DLL) to continuously adjust the timing of internal clock signals based on the actual delay path length. The clock generator dynamically opens and closes the clock window based on measured delay characteristics, adapting the window size to actual operating conditions rather than using a fixed conservative window, thereby reducing power consumption while maintaining reliability
Solution Approach 2:
The patent employs feedback mechanisms through the DLL circuit that measures the actual delay experienced by clock signals and uses this information to adjust the clock generation timing. The DLL monitors the delay path and provides feedback to the clock controller to optimize the clock window, ensuring it is neither too long (wasting power) nor too short (compromising reliability)
2Use of energy by moving object
If the clock signal generation window is shortened to reduce power consumption, then the power efficiency is improved, but the reliability and speed of memory access may be compromised
Solution Approach 1:
The patent replaces conservative timing margins with an active measurement and control system. Instead of relying on fixed timing buffers that guarantee reliability but waste time and power, the system uses DLL-based delay measurement and active clock window control to dynamically determine the minimum necessary window duration, substituting passive timing margins with active intelligent control
Solution Approach 2:
The patent changes the timing parameters of clock signal generation dynamically based on measured delay characteristics. The DLL measures actual delay values and uses this information to adjust the clock window duration and positioning, transforming static timing parameters into dynamic variables that optimize both power consumption and reliability
3Adaptability or versatility
If conservative timing windows are used to accommodate device variations and delays, then the adaptability to different operating conditions is improved, but the productivity and speed of memory access are reduced
Solution Approach 1:
The patent performs preliminary measurement of the delay path length using the DLL circuit during initialization or calibration phases. This preliminary action allows the system to know the actual delay characteristics before normal operation begins, enabling optimized clock window settings from the start rather than relying on conservative estimates that slow down operation
Data Source
AI summary
An example apparatus includes a clock input circuit to provide an internal clock signal based on an external clock signal, and a command decoder configured to provide a command signal based on a received command. The example apparatus further includes an internal clock generator having DLL circuit to receive the internal clock signal and the command signal and to provide a phase-adjusted internal clock signal based on the internal clock signal. In response to receipt of the command signal, the DLL circuit enables provision of the phase-adjusted internal clock signal to an input/output circuit and stops provision of the phase-adjusted internal clock signal after a count of clock cycles of the internal clock signal exceeds a predetermined count value. The predetermined count value is based on a signal propagation time of the internal clock signal from the output of the internal clock circuit to an output of the input/output circuit.