DLL Clocking Architecture for Coherent DVFS Frequency Scaling
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Solution Overview
Problem
Dynamic Voltage Frequency Scaling (DVFS) systems face challenges in maintaining clock coherence during frequency changes, leading to potential cycle slips and system malfunctions due to insertion delay mismatches between phase-locked loops (PLLs) and delay-locked loops (DLLs), which can cause unpredictable logical states and chip malfunctions.
Innovation Solution
A dual-PLL and DLL-based clock architecture that locks DLLs at a low start-up frequency, gradually increasing to the target frequency, ensuring matched insertion delays and preventing cycle slips by aligning clocks to the same edge of the reference clock, thereby maintaining clock coherence throughout the frequency scaling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DLL locks at high target frequency during DVFS, then frequency scaling performance is improved, but insertion delay mismatch causes cycle slips and clock coherence loss
Solution Approach 1:
The DLL is locked at a low start-up frequency before the chip is released from reset, establishing proper phase alignment and matched insertion delays between delay line paths before high-frequency operation begins. This preliminary low-frequency locking prevents cycle slips when transitioning to higher frequencies during DVFS.
Solution Approach 2:
The system dynamically adjusts the clock frequency in stages, transitioning from a low start-up frequency to a higher target frequency through controlled frequency scaling. The DLL maintains lock across frequency transitions by using the phase information established at the lower frequency as a reference for the higher frequency operation.
2Speed
If chip is released from reset before DLL locking, then reset sequence speed is improved, but clock coherence cannot be established leading to system malfunction
Solution Approach 1:
The DLL locking process is initiated and completed at a low start-up frequency before the chip is released from reset. This ensures that the clocking infrastructure is stable and coherent before the rest of the chip becomes operational, preventing system malfunction while maintaining a relatively fast reset sequence.
3Adaptability or versatility
If DLL uses variable delay line path for frequency adjustment, then frequency adaptability is improved, but insertion delay mismatch with fixed delay line path causes cycle slips
Solution Approach 1:
The variable delay line path is pre-adjusted at the low start-up frequency to match the insertion delay of the fixed delay line path before high-frequency operation. This preliminary delay matching establishes proper phase alignment that persists through frequency transitions, preventing cycle slips while maintaining frequency adaptability.
Solution Approach 2:
The DLL uses feedback from the phase detector to continuously adjust the variable delay line path, ensuring that the insertion delay matches the fixed delay line path across different operating frequencies. This feedback mechanism maintains clock coherence while allowing frequency adaptation during DVFS operations.
Data Source
AI summary
A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.