Master-Slave DLL Clocking for De-Serializer Phase Alignment
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Solution Overview
Problem
Providing a proper clock signal to de-serializers in integrated circuit (IC) dies for accurate sampling of serial data into parallel data remains a challenge in circuit design, especially in 2.5D semiconductor packaging where precise phase adjustment is essential for correct data serialization and deserialization.
Innovation Solution
A circuit incorporating a slave delay lock loop (DLL) and a master DLL is used to receive an input clock and output a control signal to adjust the delay of the sampling clock, ensuring proper phase alignment for de-serialization, with the master DLL replicating the slave DLL circuit and employing loop detection to determine the control signal for optimal clock adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple clock distribution circuit is used, then device complexity is reduced, but manufacturing precision of clock phase alignment deteriorates
Solution Approach 1:
The patent implements a delay-locked loop (DLL) circuit that uses feedback mechanisms to automatically adjust and lock the clock phase. The DLL monitors the clock signal phase and dynamically adjusts delay elements to achieve precise phase alignment, resolving the contradiction by providing automatic phase correction without requiring complex manual calibration circuits.
Solution Approach 2:
The DLL circuit is designed to self-adjust the clock phase alignment automatically. The circuit contains self-calibration functionality that enables it to find and maintain the optimal phase relationship between clock signals without external intervention, thereby achieving high precision phase alignment while keeping the overall circuit design relatively simple.
2Manufacturing precision
If a complex clock adjustment circuit is used, then manufacturing precision of clock phase alignment is improved, but device complexity increases
Solution Approach 1:
The patent employs dynamic delay adjustment mechanisms within the DLL circuit that can adaptively change delay values based on real-time phase detection. This dynamic approach allows the circuit to achieve precise phase alignment through controlled variable delays rather than requiring multiple fixed delay stages, thereby reducing overall circuit complexity while maintaining high precision.
Solution Approach 2:
The DLL circuit changes the delay parameter dynamically to achieve phase alignment. By adjusting the delay value as a controllable parameter rather than using fixed physical delay elements, the circuit achieves precise phase control with fewer components, resolving the contradiction between precision and complexity.
3Manufacturing precision
If manual clock phase calibration is used, then manufacturing precision is improved, but ease of operation deteriorates
Solution Approach 1:
The DLL circuit incorporates automatic self-calibration functionality that eliminates the need for manual clock phase adjustment. The circuit autonomously detects phase errors and adjusts delay elements to achieve alignment, thereby maintaining high precision while dramatically improving ease of operation through complete automation.
Solution Approach 2:
The automatic calibration is achieved through feedback mechanisms that continuously monitor clock phase relationships and adjust delay parameters accordingly. This closed-loop control system replaces manual calibration operations with automated feedback-driven adjustment, resolving the contradiction between precision and ease of operation.
Data Source
AI summary
A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.