DLL Clocking Scheme for Constant Non-Overlap in Pipelined ADCs
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in pipelined analog-to-digital converters (ADCs) face challenges in maintaining a constant non-overlap period across varying clock periods, temperatures, and processes, leading to increased power consumption due to amplifier currents and inefficient power scaling.
Innovation Solution
The proposed DLL design includes a phase detector, charge pump with distinct current sources and switches, and a delay line with fewer buffers, which generates clock signals to maintain a constant non-overlap period, reducing amplifier currents and power consumption by allowing faster power scaling with increasing clock periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL with multiple delay elements is used to generate non-overlapping clock signals, then the clock signals can be generated with proper timing, but the power consumption increases significantly due to amplifier currents required to maintain constant non-overlap period across process and temperature variations
Solution Approach 1:
The patent changes the parameter of current consumption by making the first current source consume less current than the second current source. Specifically, the first current source provides a current that is the difference between a generally constant current and the second current source's current, thereby reducing overall power consumption while maintaining reliable clock signal generation with constant non-overlap period across process and temperature variations.
2Manufacturing precision
If the number of delay elements in DLL is increased to achieve precise timing control, then the timing accuracy improves, but the device complexity and power consumption increase
Solution Approach 1:
The patent extracts or removes the loop filter component from the conventional DLL structure. By eliminating the loop filter, the design achieves timing control through the asymmetric current sources and simplified delay elements, thereby reducing device complexity and power consumption while maintaining adequate timing accuracy for the ADC application.
3Reliability
If amplifier current is increased to maintain acceptable bandwidth and settling error, then the settling performance improves, but the power consumption increases significantly
Solution Approach 1:
The patent changes the current parameter by implementing asymmetric current sources where the first current source consumes less current than the second current source. This parameter change allows the MDAC amplifiers to achieve acceptable settling performance and bandwidth while significantly reducing power consumption compared to conventional designs that use equal high-current sources.
Data Source
AI summary
Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount of power. Here, a DLL is provided with a modified charge pump that allows for reduced power consumption.