Delay-Locked Loop Coarse Delay Selection Under PVT Variation
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Solution Overview
Problem
Dynamic random access memory (DRAM) delay-locked loop (DLL) circuits face a conflict between resolution and locking time due to fixed unit coarse delays, which are affected by clock frequency and process, voltage, and temperature (PVT) variations, leading to inconsistent performance across different corners.
Innovation Solution
Implementing a frequency detector and unit coarse delay selector within the DLL circuit to dynamically select the appropriate unit coarse delay based on detected clock frequency and PVT conditions, ensuring a stable and uniform coarse delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If smaller unit coarse delay is used, then DLL resolution is improved, but locking time increases
Solution Approach 1:
The patent implements a unit coarse delay selector that dynamically adjusts the unit coarse delay value based on detected clock frequency and process conditions. Instead of using a fixed unit coarse delay, the system selects from multiple predetermined values (e.g., first, second, third unit coarse delays) to optimize both resolution and locking time under different operating conditions.
Solution Approach 2:
The patent changes the parameter of unit coarse delay from a fixed value to a variable that can be selected from multiple predetermined values. The unit coarse delay selector responds to detection results by selecting appropriate delay values, thereby adapting the system parameters to resolve the contradiction between resolution and locking time.
2Reliability
If different unit coarse delays are selected for different clock frequencies, then DLL performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the unit coarse delay into multiple predetermined values (first unit coarse delay, second unit coarse delay, third unit coarse delay, etc.). Each segment corresponds to a specific clock frequency range or process condition, allowing the system to select the appropriate segment without requiring complex continuous adjustment mechanisms.
Solution Approach 2:
The patent introduces a unit coarse delay selector as an intermediary component between the frequency detector and the delay elements. This selector acts as a mediator that translates detection results into appropriate delay selections, simplifying the overall control architecture while achieving adaptive performance.
3Device complexity
If unit coarse delay is fixed, then device complexity is reduced, but resolution degradation occurs under PVT variation
Solution Approach 1:
The patent prepares multiple predetermined unit coarse delay values in advance, corresponding to different process corners and frequency conditions. The unit coarse delay selector has these values ready and can quickly switch between them based on detection results, avoiding the need for complex real-time calculation or adjustment mechanisms.
Data Source
AI summary
A delay-locked loop circuit and a selection method of unit coarse delay are provided. The delay-locked loop circuit includes a frequency detector and a unit coarse delay selector. The frequency detector receives a reset signal and a clock signal. The frequency detector performs a sampling operation to detect a clock frequency of the clock signal based on a time shift of the reset signal and a sequential delay of the reset signal to generate a plurality of determining signals. The unit coarse delay selector selects one of the plurality of determining signals with an earliest transition time as a selected coarse delay signal to control a timing of the delay-locked loop circuit.