Delay-Locked Loop Coarse-Fine Switching for Faster Phase Lock
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Solution Overview
Problem
Conventional delay locked loop circuits require a significant amount of time to adjust and lock the delay signal when operational parameters such as temperature, voltage, or frequency change, leading to potential errors and non-conformance with semiconductor memory device standards.
Innovation Solution
A delay locked loop circuit with an error decision unit that dynamically switches between coarse and fine delay lines based on phase detection signals and error detection, allowing for swift and stable operation by adjusting the delay control signals and decision modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay locked loop circuits adjust delay signals when operational parameters change, then phase synchronization is maintained, but locking time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the delay signal using the coarse delay line before fine-tuning is needed. When operational parameters change, the circuit first performs a coarse adjustment to quickly bring the phase difference within an acceptable range, then performs fine adjustment to achieve precise locking. This two-stage approach prevents the need for lengthy single-stage adjustments, thereby reducing overall locking time while maintaining phase synchronization reliability.
Solution Approach 2:
The patent segments the delay adjustment process into two distinct stages: coarse delay adjustment and fine delay adjustment. The coarse delay line handles large-range adjustments for rapid initial synchronization, while the fine delay line handles small-range adjustments for precise phase matching. This segmentation allows the system to efficiently navigate the delay adjustment range, significantly reducing the time required to achieve lock compared to a single-stage adjustment mechanism.
2Measurement precision
If fine delay line is used for precise adjustment, then phase locking precision is improved, but adjustment time increases when operational parameters change
Solution Approach 1:
The patent divides the delay adjustment function into two segments: a coarse delay line for rapid, large-range adjustments and a fine delay line for precise, small-range adjustments. When operational parameters change, the coarse delay line first performs a quick adjustment to bring the phase difference within the fine delay line's effective range, after which the fine delay line completes the precise locking. This segmentation enables the system to achieve high precision without requiring the fine delay line to perform the entire adjustment range, thereby minimizing adjustment time.
Solution Approach 2:
The coarse delay line performs preliminary action by making initial large-range adjustments before the fine delay line engages. This preliminary adjustment reduces the phase difference to a level where the fine delay line can efficiently complete the precise locking, avoiding the time-consuming scenario where the fine delay line must perform the entire adjustment range from scratch.
3Device complexity
If delay signal adjustment is performed without error detection, then circuit complexity is reduced, but DLL operation errors occur under varying operational conditions
Solution Approach 1:
The patent implements feedback through an error detection unit that continuously monitors the delay signal and phase difference. When operational parameters change, the error detection unit detects deviations from the locked state and generates error signals that trigger re-adjustment of the delay signal. This feedback mechanism ensures reliable DLL operation under varying conditions without requiring overly complex control logic, as the feedback automatically initiates corrections when needed.
Solution Approach 2:
The error detection unit enables the DLL circuit to self-correct when operational parameters change. By automatically detecting errors in the delay signal and triggering appropriate adjustments, the system serves itself without requiring external intervention or overly complex control mechanisms. This self-service approach maintains reliability while keeping the overall circuit complexity manageable.
Data Source
AI summary
A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection.