Delay Locked Loop Circuit with Coarse-Fine Phase Synchronization
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Solution Overview
Problem
In semiconductor apparatuses, asynchronous delays between internal clock signals and system clock signals can lead to phase discrepancies, which existing delay locked loop circuits struggle to fully synchronize, affecting data communication efficiency.
Innovation Solution
A delay circuit comprising a coarse delay circuit, a fine delay circuit, a phase mixing circuit, and a delay control circuit, which collectively adjust and synchronize clock signals by varying delay times and phase mixing to align internal clock signals with system clock signals, using coarse and fine control signals to achieve precise phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional delay locked loop circuit is used to compensate for asynchronous delay, then some phase synchronization is achieved, but the phase discrepancy cannot be fully synchronized due to limited delay adjustment granularity
Solution Approach 1:
The delay locked loop circuit is divided into a coarse delay circuit for large-scale phase adjustment and a fine delay circuit for precise phase adjustment. This segmentation allows the system to achieve both wide adjustment range and high precision synchronization by combining two specialized delay modules with different granularities.
Solution Approach 2:
The circuit dynamically switches between coarse and fine delay modes based on the phase error magnitude. When large phase discrepancy exists, the coarse delay circuit is activated for rapid correction; when phase error is small, the fine delay circuit takes over for precise alignment, optimizing both response time and synchronization accuracy.
2Productivity
If internal clock signals are generated through various internal circuits, then the semiconductor apparatus can perform data processing, but asynchronous delay occurs causing phase discrepancy with system clock signal
Solution Approach 1:
A phase detector continuously monitors the phase difference between the internal clock signal and the system clock signal, providing feedback to the delay locked loop circuit. This feedback mechanism enables real-time detection and correction of phase discrepancies, ensuring continuous synchronization despite the asynchronous nature of internally generated clock signals.
Solution Approach 2:
The delay locked loop circuit proactively compensates for asynchronous delay by continuously adjusting the phase of internal clock signals before they are used for data processing. This preliminary phase alignment ensures that clock signals are synchronized with the system clock before entering critical data communication paths.
Data Source
AI summary
A delay circuit includes a coarse delay circuit, a header circuit, and a phase mixing circuit. The coarse delay circuit is configured to delay a reference clock signal to generate a first clock signal and a second clock signal and to change each phase of the first clock signal and the second clock signal by double a unit phase. The header circuit is configured to receive the first clock signal and the second clock signal and to generate a first phase clock signal and a second phase clock signal, between which a phase difference corresponds to half of the unit phase. The phase mixing circuit is configured to mix phases of the first phase clock signal and the second phase clock signal to generate an output clock signal.