Delay Locked Loop Switching Between Coarse and Fine Delay Modes
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Solution Overview
Problem
Conventional delay locked loop circuits require a significant amount of time to adjust and lock the delay signal when operational parameters such as temperature, voltage, or frequency change, leading to potential errors and non-compliance with semiconductor memory device standards.
Innovation Solution
A delay locked loop circuit with an error decision unit that dynamically switches between coarse and fine delay lines based on phase detection signals and error detection, allowing for swift and stable operation by adjusting the delay control signals and decision modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the conventional DLL circuit uses a single delay line for DLL operation, then the circuit structure is simple, but the locking time increases significantly when operational parameters change
Solution Approach 1:
The delay line is segmented into multiple delay lines with different delay characteristics. The system switches between these segmented delay lines based on operational conditions to achieve fast locking without excessive complexity.
Solution Approach 2:
The system dynamically switches between different delay lines based on detected operational parameter changes. This dynamic adaptation allows the DLL to maintain fast locking performance across varying conditions without requiring a permanently complex structure.
2Measurement precision
If the DLL operation is carried out using only the fine delay line, then the delay locking precision is high, but the locking time becomes excessively long when operational parameters change
Solution Approach 1:
The delay adjustment function is segmented into coarse and fine components. The coarse delay line provides rapid initial adjustment while the fine delay line provides precise final adjustment, combining speed and precision.
Solution Approach 2:
The coarse delay line performs preliminary delay adjustment before the fine delay line takes over for precise locking. This preliminary action reduces the initial phase difference significantly, allowing the fine delay line to complete locking quickly.
3Device complexity
If the DLL circuit does not detect delay mode errors, then the circuit operation is simple, but errors occur when operational parameters change causing non-compliance with standards
Solution Approach 1:
The error detection unit provides feedback about delay mode correctness based on phase detection signals. This feedback mechanism ensures reliable operation under varying conditions without requiring overly complex control logic.
Solution Approach 2:
The system automatically detects and corrects delay mode errors through the error detection unit and control unit, enabling self-service operation that maintains reliability without excessive complexity.
Data Source
AI summary
A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection.