Digital DLL Coarse Lock Estimation for Low-Power DQS Alignment
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Solution Overview
Problem
Conventional DDR memory interfaces face challenges in aligning data strobe (DQS) signals with the system clock, leading to timing inaccuracies, especially at higher frequencies, and existing DLL architectures consume significant power and are sensitive to phase detectors, which can result in false locking and noise sensitivity.
Innovation Solution
An open-loop measurement-based technique is employed to determine the coarse delay code for the DLL circuit, allowing it to operate in an open-loop mode for coarse lock positioning and then switch to a closed-loop mode for tracking, reducing the reliance on phase detectors and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL architectures with phase detectors are used, then locking functionality is provided, but power consumption increases and noise sensitivity increases
Solution Approach 1:
The patent extracts and removes the phase detector component from the DLL architecture, transitioning from a closed-loop design to an open-loop design. This extraction eliminates the primary source of power consumption and noise sensitivity while preserving the essential delay locking functionality through alternative measurement-based techniques.
Solution Approach 2:
The DLL circuit performs self-measurement of delay values using measurement circuits that are integrated within the same circuit. This self-service approach eliminates the need for external phase detectors and enables the circuit to determine its own delay characteristics, reducing power consumption and noise sensitivity.
2Reliability
If phase detectors are used in DLL circuits, then locking control is provided, but false locking occurs and noise sensitivity increases
Solution Approach 1:
The patent replaces the phase detector-based control mechanism with a measurement-based open-loop control mechanism. Instead of using phase detection circuits that are susceptible to noise and false locking, the system uses delay value measurements and digital control to achieve locking, fundamentally substituting the control paradigm to eliminate noise sensitivity.
Solution Approach 2:
The patent introduces measurement circuits as intermediaries between the delay elements and the control logic. These measurement circuits provide accurate delay information without the noise and false locking issues of phase detectors, acting as a mediator that enables reliable control through alternative means.
3Measurement precision
If closed-loop mode is used for DLL operation, then tracking accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic operating mode that allows the DLL to switch between open-loop and closed-loop operation. The system operates in open-loop mode for power-efficient delay adjustment and transitions to closed-loop mode only when tracking accuracy is required, optimizing the trade-off between power consumption and tracking precision based on operational needs.
Solution Approach 2:
The patent segments the DLL operation into distinct phases: coarse delay adjustment in open-loop mode and fine tracking in closed-loop mode. This segmentation allows the system to spend most time in the lower-power open-loop state while maintaining the capability to switch to high-precision closed-loop operation when necessary.
Data Source
AI summary
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.