DLL Access Command Timing Alignment for Memory Data Latching
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Solution Overview
Problem
In memory devices, particularly three-dimensional cross-point memory and threshold-type memories, there is a challenge in aligning access commands with the correct timing across different clock domains, leading to potential delays and misalignment of data transmission between the storage and device time domains.
Innovation Solution
The implementation of delay locked loop (DLL) circuitry to align access commands, such as write commands, by applying similar delays as those experienced by the reference clock signal, ensuring that both the command and clock signals are synchronized, thereby improving timing alignment and reducing the likelihood of early or late latching of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If access commands are transmitted without delay adjustment, then device complexity is reduced, but timing alignment between commands and data clock signals deteriorates
Solution Approach 1:
A delay adjustment circuit is introduced as an intermediary component between the command transmission path and the data clock signal path. This circuit applies a configurable delay to the access command, allowing it to be synchronized with the data clock signal without requiring fundamental changes to the memory device architecture.
Solution Approach 2:
The delay adjustment circuit modifies the timing parameter of the access command by applying a variable delay. This delay can be programmed to match the specific timing requirements of different memory operations, enabling precise alignment with the data clock signal while maintaining flexibility across various operating conditions.
2Reliability
If delay adjustment circuitry is added to align access commands, then timing alignment improves, but device complexity increases
Solution Approach 1:
The delay adjustment circuit serves as a mediator that improves timing synchronization between access commands and data clock signals. By isolating the complexity to this dedicated circuit, the rest of the memory device maintains its original simple architecture while still achieving reliable timing alignment.
Solution Approach 2:
The delay adjustment circuit is designed to be universally applicable to various types of access commands and memory operations. A single circuit can be configured to handle different timing requirements, reducing the need for multiple specialized circuits and thereby minimizing the overall increase in device complexity.
3Measurement precision
If access commands are delayed to match data clock timing, then data latching accuracy improves, but command transmission speed decreases
Solution Approach 1:
The delay adjustment circuit applies the required delay to the access command in advance, before the command reaches the memory array. This preliminary timing adjustment ensures that the command is properly synchronized with the data clock signal, allowing for accurate data latching without requiring slower transmission speeds throughout the entire command path.
Data Source
AI summary
Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.