Delay Locked Loop Control for DDR Memory Power Reduction
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Solution Overview
Problem
DDR synchronous memory devices face challenges in synchronizing data output with the rising and falling edges of the system clock due to internal delays, leading to inefficiencies and increased current consumption, particularly in varying operational modes.
Innovation Solution
A semiconductor memory device with a clock buffer, delay locked loop unit, and clock buffer control unit that synchronizes data output timing with the system clock and controls the clock buffer's on/off switching based on operational modes, such as pre-charge power down and self-refresh emulation modes, to reduce current consumption and ensure accurate synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay locked loop continuously operates to maintain accurate synchronization, then data output timing is precisely synchronized with the system clock, but current consumption increases
Solution Approach 1:
The delay locked loop operates periodically rather than continuously. The control unit determines operational modes (normal, pre-charge power down, self-refresh emulation) and activates the delay locked loop only when synchronization is needed, turning it off during power down modes to reduce current consumption while maintaining accuracy when active
Solution Approach 2:
The operational state of the delay locked loop is dynamically adjusted based on memory device operational modes. The control unit switches the delay locked loop between active and inactive states depending on whether the device is in normal operation, pre-charge power down, or self-refresh emulation mode, optimizing both performance and power consumption
2Reliability
If the clock buffer remains on to ensure continuous clock signal availability, then data synchronization is maintained, but current consumption increases during power down modes
Solution Approach 1:
The clock buffer is activated periodically based on operational mode rather than continuously. The control unit enables the clock buffer during normal operation to maintain synchronization reliability, and disables it during pre-charge power down and self-refresh emulation modes to reduce current consumption while maintaining necessary functionality
3Use of energy by moving object
If the delay locked loop is turned off to reduce current consumption, then power efficiency improves, but synchronization accuracy degrades
Solution Approach 1:
The delay locked loop's operational state is dynamically controlled based on memory device mode. During normal operation, the loop remains active to maintain high synchronization accuracy. During pre-charge power down and self-refresh emulation modes, the loop is deactivated to reduce current consumption, as precise synchronization is less critical in these states
4Use of energy by moving object
If the clock buffer is turned off to reduce current consumption, then power efficiency improves, but data output synchronization reliability decreases
Solution Approach 1:
The clock buffer's operational state is dynamically adjusted according to operational mode. It remains enabled during normal operation to ensure reliable data output synchronization, and is disabled during pre-charge power down and self-refresh emulation modes to reduce current consumption when synchronization reliability requirements are reduced
Data Source
AI summary
A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer.