Matched Charge Pump and Bias Generator for Stable DLL Control Voltage
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Solution Overview
Problem
Conventional delay lock loops face challenges in achieving a balanced charge and discharge current due to topographical differences between the charge pump, bias generator, and voltage controlled delay line, leading to asymmetrical operation and excessive charging current at low control voltage ranges.
Innovation Solution
The proposed solution involves a bias generator and charge pump design with a parallel/series transistor configuration that balances charge and discharge currents by matching the topography of the bias generator with the charge pump, and using PMOS transistors to regulate current flow, ensuring balanced charging and discharging of the capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional charge pump and bias generator designs are used with different topographies, then device functionality is achieved, but charge and discharge current balance is poor leading to asymmetrical operation
Solution Approach 1:
The patent applies homogeneity by making the charge pump and bias generator have substantially the same topography, both using PMOS transistors with identical gate control arrangements. This structural uniformity ensures that charge and discharge currents are naturally balanced, resolving the asymmetrical operation problem without adding complex control circuits.
2Reliability
If PMOS transistors are used in the charge pump, then discharge current is limited, but charging current becomes excessive at low control voltage ranges
Solution Approach 1:
The patent employs feedback by applying the control voltage to the gates of PMOS transistors in both the charge pump and bias generator. This feedback mechanism dynamically adjusts the charge and discharge currents based on the control voltage level, preventing excessive charging current at low voltage ranges while maintaining balanced operation across the full voltage range.
3Reliability
If topography matching is implemented between charge pump and bias generator, then current balance improves, but design complexity increases
Solution Approach 1:
The patent resolves the manufacturing complexity issue by using identical PMOS transistor topographies for both charge pump and bias generator. This homogeneous design simplifies the manufacturing process compared to mixing different transistor types, as it requires only one transistor type and one fabrication process, while still achieving the desired current balance and operational symmetry.
Data Source
AI summary
Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase detector and a charge pump. The charge pump can either charge or discharge a capacitor as a function of a signal from the phase detector to generate a control voltage. The bias generator can receive the control voltage from the capacitor, and it generates bias voltages corresponding thereto. A portion of the bias generator can have a topography that is substantially the same as at least a portion of the topography of the charge pump. As a result, it can cause the charge pump to charge the capacitor at the same rate that it discharges the capacitor over a relatively wide range of control voltages. The charge pump and the bias generator can also include circuitry for limiting the charging of the capacitor when the control voltage is relatively low.