Delay-Locked Loop Count Detection for Faster Clock Synchronization
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Solution Overview
Problem
High-speed electronic systems face challenges in synchronizing internal clock signals across different components due to manufacturing parameter variations, ambient temperature, and voltage changes, leading to phase differences in clock signals, which existing synchronization methods like digital delay locked loops and measure-controlled delay circuits struggle to address efficiently.
Innovation Solution
A delay-locked loop system that employs a loop counter and measure initialization process using a divide clock to detect the number of clock cycles required for synchronization, allowing for precise adjustment of the variable delay line to synchronize internal and external clock signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital delay locked loop (DDLL) circuit is used to detect phase difference between clock signals, then synchronization is achieved, but the circuit requires a relatively large number of clock cycles to synchronize
Solution Approach 1:
The patent applies preliminary action by using a measure-controlled delay (MCD) circuit to generate an initial measurement and establish a preliminary synchronization state before the DDLL circuit takes over. This preliminary delay measurement allows the system to start from a closer approximation of the correct delay value, significantly reducing the number of clock cycles needed for the DDLL to achieve final synchronization. The MCD circuit performs the initial rough alignment, and then the DDLL refines it, combining fast initial acquisition with precise final locking.
2Measurement precision
If manufacturing parameters and ambient conditions are considered for synchronization, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by designing a feedback mechanism where the DDLL circuit automatically detects phase differences and adjusts its own delay elements without external intervention. The circuit monitors its own synchronization status and self-corrects timing deviations caused by manufacturing variations and ambient conditions. This self-adjusting capability allows the system to maintain high timing precision while avoiding the need for complex external calibration equipment or manual adjustment mechanisms.
Solution Approach 2:
The patent implements feedback through the DDLL architecture where the output clock signal is fed back to be compared with the reference clock signal. The phase detector continuously monitors the phase difference between these signals and generates error signals that are fed back to control the delay elements. This closed-loop feedback mechanism automatically compensates for timing drifts caused by temperature changes, voltage variations, and manufacturing tolerances, maintaining synchronization accuracy without requiring complex external control systems.
Data Source
AI summary
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.