Delay Locked Loop Cycle Counting for Clock Alignment
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Solution Overview
Problem
In high-speed memory systems, accurately determining the number of clock cycles of delay through a delay locked loop is challenging due to variations in delay caused by temperature, voltage, and processing changes, which can lead to misalignment of data and clock signals, affecting data transmission accuracy.
Innovation Solution
The method involves injecting a skipped cycle into the periodic signal within the delay locked loop, allowing for the detection of the number of clock cycles of delay without disrupting the loop's operation, thus maintaining minimal interference and ensuring accurate phase alignment during data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a skipped cycle is injected into the periodic signal to determine the number of clock cycles of delay, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies periodic action by injecting a skipped cycle (a periodic disturbance) into the clock signal to propagate through the delay locked loop. This periodic injection allows the system to measure the number of clock cycles of delay by detecting when the skipped cycle exits the loop, providing precise measurement without requiring complex additional circuitry.
Solution Approach 2:
The skipped cycle acts as an intermediary signal that carries measurement information through the delay locked loop. By injecting this intermediate signal and detecting its exit point, the system can determine the delay cycle count without directly measuring the delay itself, thus simplifying the overall measurement mechanism.
2Speed
If the delay locked loop operates at high clock frequencies with short periods, then speed is improved, but measurement precision deteriorates because the total delay can be longer than a single clock period
Solution Approach 1:
The patent applies preliminary action by injecting the skipped cycle into the running delay locked loop before the measurement is needed. This allows the skipped cycle to propagate through the entire delay path in advance, and the system can determine the delay cycle count by detecting when this pre-injected cycle exits the loop, ensuring accurate measurement even at high frequencies where multiple cycles fit within the delay period.
Data Source
AI summary
Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.