Delay Locked Loop Cycle Counting for Precise Clock Delay Alignment
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Solution Overview
Problem
In high-speed memory systems, accurately determining the number of clock cycles of delay through a delay locked loop is challenging due to varying delays caused by temperature, voltage fluctuations, and processing variations, which can lead to misalignment of data and clock signals, affecting data transmission accuracy.
Innovation Solution
Injecting a skipped cycle into the periodic signal within the delay locked loop allows for the determination of the number of clock cycles of delay with minimal interference, maintaining the loop's locked state and avoiding the need for repeated locking, thus minimizing impact on the delay characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay locked loop is stopped to measure delay, then measurement accuracy is improved, but loop stability deteriorates and repeated locking is required
Solution Approach 1:
A cycle counter is introduced as an intermediary component that counts clock cycles without requiring the delay locked loop to be stopped. The counter operates independently while the loop remains locked, allowing continuous measurement without disrupting loop stability.
Solution Approach 2:
The cycle counter is initialized and ready to count before any measurement is needed. By pre-positioning the counter in a ready state and using it to track clock cycles continuously, the system avoids the need to stop and restart the loop for each measurement.
2Measurement precision
If traditional delay measurement methods are used, then delay characteristics can be determined, but the loop must be repeatedly locked which increases time consumption
Solution Approach 1:
The cycle counter operates continuously without interruption, counting clock cycles as they occur. This continuous operation eliminates the need to stop and restart the delay locked loop for each measurement, significantly reducing the time required for delay determination while maintaining measurement accuracy.
3Measurement precision
If a skipped cycle is injected into the periodic signal, then the number of clock cycles of delay can be determined with minimal interference, but the signal integrity may be affected
Solution Approach 1:
The cycle counter serves as an intermediary that detects the skipped cycle without requiring actual signal manipulation. By counting clock cycles and detecting the absence of one cycle, the system determines delay characteristics while maintaining signal integrity and periodicity.
Data Source
AI summary
Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.