DLL and DCC Tracking for Low-Power Clock Synchronization
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Solution Overview
Problem
Synchronous semiconductor memories face challenges in maintaining clock synchronization due to variations in external clock frequency and supply voltage, leading to inefficiencies in power consumption and tracking accuracy.
Innovation Solution
The implementation of low-power DLL and DCC tracking circuits that monitor clock frequency, duty cycle, and supply voltage variations, enabling dynamic adjustment of clock signals to maintain phase and duty cycle alignment, using circuits with non-overlapping clock generators, charge pumps, and comparison circuits to determine tracking enablement based on threshold values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DLL tracking is left on at all times to compensate for external clock variations, then clock synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic tracking enablement by monitoring supply voltage and clock frequency variations in real-time. The DLL tracking function is dynamically enabled or disabled based on whether monitored parameters exceed predefined thresholds, allowing the system to adapt its power consumption and synchronization accuracy to current operating conditions
Solution Approach 2:
The system changes the operational state of the DLL tracking circuit based on parameter thresholds. When supply voltage or clock frequency variations remain within acceptable ranges, tracking is disabled to save power. When variations exceed thresholds, tracking is enabled to maintain synchronization accuracy, thus dynamically adjusting system behavior based on parameter changes
2Use of energy by moving object
If DLL tracking is periodically enabled based on device activity, then power consumption is reduced, but clock synchronization reliability deteriorates
Solution Approach 1:
The patent employs feedback mechanisms by continuously monitoring supply voltage and clock frequency and using this information to control the DLL tracking enablement. This closed-loop approach ensures tracking is enabled only when actual variations warrant it, maintaining reliability while avoiding unnecessary power consumption from speculative tracking
Solution Approach 2:
The system performs self-monitoring of its operating conditions and autonomously decides when tracking should be enabled or disabled. The memory device itself detects variations in its environment and adjusts its own tracking behavior, eliminating the need for external control or speculative tracking based on activity patterns
3Use of energy by moving object
If determined delay is applied without continuous tracking, then power consumption is reduced, but phase alignment accuracy deteriorates due to clock and voltage variations
Solution Approach 1:
Instead of continuous tracking, the system employs periodic tracking enabled only when variations in supply voltage or clock frequency exceed predefined thresholds. This selective periodic action maintains phase alignment accuracy during critical variations while consuming minimal power during stable operating conditions
Data Source
AI summary
Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.