DLL Delay Cell Control for Wide-Range Memory Clock Locking
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Solution Overview
Problem
Semiconductor memory devices face high current consumption when operating over a wide frequency range due to the need for multiple delay cells to be turned on, which increases power usage and heat generation.
Innovation Solution
A semiconductor memory device with a delay lock loop (DLL) that selectively turns on a predetermined number of delay cells based on a threshold frequency recognition signal, using a controller to generate signals for reducing current consumption and increasing delay time, and includes features like registers for on-state information, clock delay units, selection units, and a phase interpolation unit to generate an internal clock signal with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a greater number of delay cells are turned on to perform locking operation at low frequency, then the frequency range of DLL is extended, but current consumption of DLL increases
Solution Approach 1:
The DLL is divided into multiple delay cells that can be independently controlled. The controller selectively activates only the necessary number of delay cells based on the operating frequency, rather than keeping all cells active. This segmentation allows the system to adapt to different frequency ranges while minimizing current consumption by excluding unnecessary cells from operation.
Solution Approach 2:
The DLL configuration is made dynamic through the controller that adjusts the number of active delay cells according to the operating frequency. At low frequencies, more cells are activated to achieve the required phase shift range, while at high frequencies, fewer cells are sufficient. This dynamic adaptation resolves the contradiction between frequency range and current consumption.
2Adaptability or versatility
If more delay cells are turned on to extend frequency range, then locking operation capability is improved, but power consumption increases
Solution Approach 1:
The delay cells are segmented into independently controllable units with individual on/off control signals. This allows the controller to activate only the specific number of cells needed for the current operating frequency, extending the locking range when necessary while minimizing power consumption by keeping other cells inactive.
Solution Approach 2:
The system changes the operational parameters by adjusting the number of active delay cells based on frequency requirements. The controller modifies the state of delay cells (active/inactive) as a parameter change, enabling the DLL to achieve wide frequency range coverage while maintaining low power consumption at each operating point.
3Speed
If delay cells are turned on for high speed locking operation, then locking speed is improved, but current consumption increases
Solution Approach 1:
The system applies partial action by activating only the necessary number of delay cells required for achieving high-speed locking at the current frequency, rather than keeping all cells active. This partial activation maintains the high-speed locking capability when needed while reducing current consumption by excluding excess cells from operation.
Data Source
AI summary
A semiconductor memory device includes a delay lock loop (DLL) performing a locking operation at a wide frequency range and reducing current consumption. The semiconductor memory device includes a (DLL) having serially connected delay cells that receive and delay an external clock signal, wherein a predetermined number of delay cells of the serially connected delay cells that are to perform a delay operation are turned on in response to a threshold frequency recognition signal and first and second delay cell on signals, and for generating an internal clock signal; and a controller for generating the threshold frequency recognition signal and the first and second delay cell on signals, which reduce current consumption of each of the serially connected delay cells and increase a period of delay time thereof, if more delay cells are to be turned on when a delay cell indicating a threshold frequency is turned on.