DLL Delay Chain Reconfiguration for Reduced Duty Cycle Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay-locked loop (DLL) circuits face challenges in achieving a reliable phase shift over a wide frequency range, particularly for double data rate (DDR) memory applications, due to limitations in phase options and duty cycle distortion, which are exacerbated by constraints across process, supply voltage, and temperature (PVT) corners.
Innovation Solution
A DLL circuit design incorporating 8 delay circuit elements with a phase detector, up/down counter, and frequency divider circuits, where each delay circuit element has adjustable delay blocks controlled by Gray coded count signals to maintain a consistent delay and reduce duty cycle distortion through a dynamically controlled delay chain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a delay line circuit uses a fixed number of delay circuits to provide phase shift, then the circuit structure is simple, but the frequency range support is limited and phase options are insufficient
Solution Approach 1:
The patent implements a dynamically controlled delay chain where the number of active delay circuits is adjustable. The delay line includes multiple delay circuits (10-25) that can be selectively enabled or disabled based on the desired phase shift and frequency requirements. This dynamic configuration allows the circuit to adapt to different frequency ranges and phase options without requiring a completely different circuit structure for each application.
Solution Approach 2:
The delay line is segmented into multiple individual delay circuits (10-25) that can be independently controlled. Each delay circuit provides a specific delay amount, and by selectively enabling different combinations of these segmented delay circuits, the circuit can achieve various phase shifts and support a wide frequency range. This segmentation transforms a fixed-structure limitation into a flexible, reconfigurable system.
2Manufacturing precision
If delay circuits are used to provide phase shift, then phase adjustment is achieved, but duty cycle distortion accumulates across the delay chain
Solution Approach 1:
The patent employs an even number of inverting delay circuit elements in the delay chain. Each inverting element contributes to duty cycle distortion, but by using an even number, the distortions from individual elements cancel each other out, resulting in reduced overall duty cycle distortion at the output. This approach converts the harmful effect of individual element distortion into a beneficial cancellation effect.
Solution Approach 2:
The patent changes the parameter of the delay chain by ensuring an even number of inverting elements and dynamically adjusting which delay circuits are active. This parameter change optimizes the duty cycle preservation while maintaining the required phase shift accuracy. By controlling the number and configuration of active delay circuits, the system achieves both precise phase adjustment and reduced duty cycle distortion.
3Adaptability or versatility
If the number of delay circuits is increased to support wide frequency range, then frequency flexibility improves, but circuit complexity and PVT constraint management become more difficult
Solution Approach 1:
The patent implements dynamic control of the delay chain configuration through a controller that receives feedback from a phase detector. The controller selectively enables or disables delay circuits based on the detected phase difference and the desired frequency range. This dynamic adaptation allows the system to maintain optimal performance across wide frequency ranges without requiring manual reconfiguration or complex fixed structures.
Solution Approach 2:
The patent incorporates a phase detector and controller that form a feedback loop. The phase detector monitors the phase difference between the reference clock signal and the delayed feedback signal, and the controller adjusts the active delay circuits accordingly. This feedback mechanism automatically compensates for PVT variations and maintains accurate phase shifting across different frequency ranges, reducing the complexity of manual PVT constraint management.
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable and fixed delay blocks inverts a received signal to generate an inverted signal.