DLL Delay Chain Grouping for Low-Power Duty Cycle Correction
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Solution Overview
Problem
Existing DLL circuits require a large number of phase comparators, leading to increased leakage current, power consumption, and layout area due to the need for one phase comparator per delay element, which complicates high-speed locking in applications like NAND type flash memory.
Innovation Solution
The semiconductor integrated circuit groups delay elements into matrices, reducing the number of phase comparators required by detecting delay element stages in two stages: specifying groups and then elements within those groups, thereby minimizing the number of phase comparators needed for delay time detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If one phase comparator is provided per delay element to detect delay time accurately, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The delay chain is divided into multiple groups, with each group containing several delay elements. Instead of providing one phase comparator per delay element, a single phase comparator is shared among multiple delay elements within the same group. The detection is performed in two stages: first specifying the group, then specifying the delay element within that group, thereby reducing the total number of phase comparators while maintaining detection precision.
Solution Approach 2:
A single phase comparator is designed to serve multiple delay elements by being reused across different groups and delay elements through controlled activation. The phase comparator functions universally for detecting delay times of multiple delay elements by selecting which delay element to compare based on control signals, eliminating the need for dedicated phase comparators for each delay element.
2Measurement precision
If one phase comparator is provided per delay element to ensure accurate delay detection, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The delay chain is divided into multiple groups, with each group containing several delay elements. Instead of providing one phase comparator per delay element, a single phase comparator is shared among multiple delay elements within the same group. The detection is performed in two stages: first specifying the group, then specifying the delay element within that group, thereby reducing the total number of phase comparators while maintaining detection precision.
Solution Approach 2:
The phase comparator is activated only when needed for specific delay element detection rather than being continuously active for all delay elements. By selectively enabling the phase comparator for specific groups and delay elements during the detection process, power consumption is reduced while maintaining the ability to accurately detect delay times when required.
3Measurement precision
If one phase comparator is provided per delay element to detect delay time accurately, then measurement precision is improved, but layout area increases
Solution Approach 1:
The delay chain is divided into multiple groups, with each group containing several delay elements. Instead of providing one phase comparator per delay element, a single phase comparator is shared among multiple delay elements within the same group. The detection is performed in two stages: first specifying the group, then specifying the delay element within that group, thereby reducing the total number of phase comparators while maintaining detection precision.
Solution Approach 2:
Multiple delay elements are merged into groups that share a common phase comparator. By combining the detection function for multiple delay elements into a single phase comparator through group-based segmentation, the total layout area is reduced while maintaining the ability to detect delay times for all delay elements in the chain.
Data Source
AI summary
According to one embodiment, in a semiconductor integrated circuit of a DLL circuit, in a delay chain, a plurality of delay elements are connected. A first detection circuit detects a group corresponding to a certain delay amount among a plurality of groups obtained by dividing the delay chain. A second detection circuit detects a delay element corresponding to the certain delay amount among a plurality of delay elements included in the detected group. The semiconductor integrated circuit detects the number of delay elements corresponding to one cycle of a first clock. The control circuit includes a second delay chain. The second delay chain has a configuration equivalent to the delay chain in the semiconductor integrated circuit. The control circuit outputs a second clock obtained by delaying the first clock by using the second delay chain according to the number of delay elements detected by the semiconductor integrated circuit.


