DLL Delay Code Scaling Across Different Clock Frequencies
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Solution Overview
Problem
In source synchronous memory systems with multiple clock domains, existing technologies face challenges in ensuring consistent delay times across different clock frequencies, as the delay code generated by a master DLL cannot be directly applied to slave DLLs operating at different frequencies.
Innovation Solution
A scaling circuitry is introduced to determine the frequency ratio between the master and slave DLLs' clock signals, generating an adjusted delay code for the slave DLLs to achieve the desired fractional delay, allowing for consistent delay times across different clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a master DLL provides delay code for slave DLLs operating at different frequencies, then delay consistency across clock domains can be achieved, but the delay code cannot be directly applied due to frequency differences
Solution Approach 1:
A scaling circuit is introduced as an intermediary component between the master DLL and slave DLLs. This scaling circuit receives the delay code from the master DLL, scales it according to the frequency ratio, and generates the appropriate delay code for slave DLLs operating at different frequencies, thereby enabling delay consistency without direct application of the master DLL's delay code
Solution Approach 2:
The delay code parameter is transformed by applying a frequency ratio scaling factor. The scaling circuit multiplies the master DLL's delay code by the ratio of slave clock frequency to master clock frequency, converting the delay code from one frequency domain to another while preserving the intended delay timing relationship
2Adaptability or versatility
If multiple slave DLLs operate at lower frequencies than the master DLL, then they can interface with different memory types, but the delay code must be adjusted for each frequency
Solution Approach 1:
The scaling circuit serves multiple slave DLLs simultaneously with different frequency requirements. By receiving a single delay code from the master DLL and applying frequency-specific scaling factors, the scaling circuit generates appropriate delay codes for multiple slave DLLs, enabling the system to interface with various memory types without requiring separate delay calibration for each slave DLL
Solution Approach 2:
Different delay code parameters are generated for each slave DLL based on their specific operating frequencies. The scaling circuit applies unique frequency ratio multipliers to the master DLL's delay code for each slave DLL, allowing each slave to operate at its optimal frequency while maintaining consistent delay timing relative to its clock domain
Data Source
AI summary
A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.