Delay Locked Loop Circuit With Delay-End Lock Termination
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Solution Overview
Problem
Register-controlled delay locked loop circuits in semiconductor memory devices face issues with infinite loop or prolonged delay locking operations due to the inability to terminate the delay locking process when the phase difference between the source and feedback clocks reaches a maximum value, leading to inefficient power consumption and potential data synchronization issues.
Innovation Solution
Incorporating a delay end signal mechanism that activates when the delay amount reaches a limit, forcing the termination of the delay locking operation and allowing the circuit to operate with an internal supply voltage to minimize power consumption and prevent infinite loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay locking operation continues until phase synchronization is achieved, then data synchronization accuracy is improved, but the operation may become infinite or excessively prolonged when maximum phase difference is reached, increasing power consumption
Solution Approach 1:
The patent applies preliminary action by establishing a maximum delay limit before the delay locking operation begins. The delay control unit is pre-configured with a maximum delay value that limits the operational range of the delay element. This prevents the operation from becoming infinite by setting a predetermined boundary, while still allowing sufficient delay range to achieve phase synchronization for most practical cases.
Solution Approach 2:
The patent implements feedback through the delay lock detection unit that continuously monitors whether phase synchronization has been achieved. When the detection unit determines that the phase difference is within the synchronized range, it generates a delay lock signal that terminates the delay locking operation. This feedback mechanism ensures the operation stops promptly upon achieving synchronization, preventing excessive duration and power consumption.
2Loss of energy
If the delay locking operation is terminated early when maximum phase difference is reached, then power consumption is reduced and infinite loops are prevented, but data synchronization accuracy may be compromised
Solution Approach 1:
The patent applies preliminary action by establishing a maximum delay limit before the delay locking operation begins. The delay control unit is pre-configured with a maximum delay value that limits the operational range of the delay element. This prevents the operation from becoming infinite by setting a predetermined boundary, while still allowing sufficient delay range to achieve phase synchronization for most practical cases.
Solution Approach 2:
The patent implements feedback through the delay lock detection unit that continuously monitors whether phase synchronization has been achieved. When the detection unit determines that the phase difference is within the synchronized range, it generates a delay lock signal that terminates the delay locking operation. This feedback mechanism ensures the operation stops promptly upon achieving synchronization, preventing excessive duration and power consumption.
3Reliability
If the delay locking operation runs indefinitely to ensure synchronization, then data synchronization reliability is improved, but the circuit complexity and control difficulty increase
Solution Approach 1:
The patent applies preliminary action by establishing a maximum delay limit before the delay locking operation begins. The delay control unit is pre-configured with a maximum delay value that limits the operational range of the delay element. This prevents the operation from becoming infinite by setting a predetermined boundary, while still allowing sufficient delay range to achieve phase synchronization for most practical cases.
Solution Approach 2:
The patent implements feedback through the delay lock detection unit that continuously monitors whether phase synchronization has been achieved. When the detection unit determines that the phase difference is within the synchronized range, it generates a delay lock signal that terminates the delay locking operation. This feedback mechanism ensures the operation stops promptly upon achieving synchronization, preventing excessive duration and power consumption.
Data Source
AI summary
The present invention relates to a delay locked loop (DLL) circuit. The DLL circuit includes a phase comparator configured to compare a phase of a source clock with a phase of a feedback clock and generate a delay locking signal based on the comparison result, a clock delay configured to delay the source clock in response to the delay locking signal for locking delay, output the delayed source clock as a delay locked clock, and generate a delay end signal when a delay amount has reached a delay limit, a delay replica model configured to reflect a delay time of an output path of the source clock at the delay locked clock and output the reflected clock as the feedback clock, and a delay locking operation controller configured to terminate a delay locking operation in response to the delay locking signal and the delay end signal.