DLL Fine Delay Interpolation for Higher Clock Frequency
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Solution Overview
Problem
Conventional delay-locked loop (DLL) circuits have a minimum operation cycle that limits the maximum operation frequency due to the need for interpolation of signals with a phase difference corresponding to at least two inverter pairs, resulting in increased latency and reduced performance in high-speed data transfer applications.
Innovation Solution
The DLL circuit is redesigned with a first and second delay circuit that reduce the phase difference between signals from two delay stages to one delay stage, allowing for interpolation by a second fine delay adjustment circuit, thereby reducing the minimum operation cycle and increasing the maximum operation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signals with a phase difference of two delay stages are used for interpolation, then the DLL circuit can achieve clock synchronization, but the minimum operation cycle increases to 12tD, limiting the maximum operation frequency
Solution Approach 1:
The patent divides the delay adjustment into two independent segments: a coarse delay circuit that provides integer-multiple delay stages (0, 1, 2, 3 stages) and a fine delay circuit that performs interpolation between selected coarse delay signals. This segmentation allows the system to achieve both reliable clock synchronization through multiple discrete delay steps and higher operation frequencies by reducing the interpolation cycle from 12tD to 6tD or less.
2Reliability
If signals with a phase difference of two delay stages are used for interpolation, then clock synchronization can be achieved, but the operation cycle increases, reducing data transfer speed
Solution Approach 1:
The patent implements dynamic delay adjustment by making the coarse delay circuit selectively output different delay stage signals (0, 1, 2, or 3 stages) based on control signals, and dynamically switching between different coarse delay taps (e.g., switching between delay stage 0 and delay stage 1) to optimize the interpolation process. This dynamic operation reduces the minimum operation cycle and enables faster data transfer while maintaining synchronization reliability.
Data Source
AI summary
A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.