Programmable DLL Delay Line for Wide-Range Low-Jitter Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Delay Locked Loops (DLLs) in high-speed serial communication links face challenges in maintaining precise phase and frequency locking due to limited timing range and high jitter, which affects the reliability of clock recovery in high-speed Ethernet connections.
Innovation Solution
A programmable delay line within the DLL is controlled by both analog and digital signals, allowing for finer control of delay by adjusting the drive current of enablable inverters, enabling a larger delay range and reduced jitter through a combination of thermometer-coded and binary-coded control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL uses traditional delay control methods, then the circuit structure is simple, but the timing range is limited and jitter is high
Solution Approach 1:
The delay line is divided into multiple delay stages, each controlled by separate digital and analog control signals. This segmentation allows independent optimization of each stage's delay characteristics, expanding the total timing range while maintaining precise control through the combination of digital (coarse) and analog (fine) adjustment mechanisms.
Solution Approach 2:
The delay amount in each stage is made dynamically adjustable through dual control signals: digital signals provide discrete step changes for coarse delay adjustment, while analog signals provide continuous variation for fine delay tuning. This dynamic control mechanism enables the delay line to adapt to varying timing requirements and reduces jitter by allowing precise phase alignment.
2Measurement precision
If a DLL uses analog control signals for delay adjustment, then the delay control precision is improved, but the power consumption increases
Solution Approach 1:
Instead of using full analog control for all delay stages, the invention applies analog control selectively to provide fine-tuning where precision is most needed, while digital control handles the majority of delay adjustment. This partial use of analog control achieves high precision without the excessive power consumption of fully analog control across all stages.
Solution Approach 2:
The invention merges digital and analog control mechanisms into a unified delay control system. Digital control signals handle coarse delay adjustment with low power consumption, while analog control signals provide fine-tuning precision only when needed. This combination achieves high measurement precision for delay control while maintaining reasonable power consumption by leveraging the strengths of both control types.
Data Source
AI summary
A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.