DLL Delay Line Testing with Low-Frequency Ring Oscillation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DLL circuits face challenges in performing normal operation tests when the frequency of the reference clock signal is high, as they require two lines of clock signals with adjusted phase differences, increasing the burden on test device accuracy and chip layout design, especially when the delay amount for the test clock signal exceeds the capabilities of the delay line circuit.
Innovation Solution
A DLL circuit configuration that includes a first delay line circuit, a phase comparison circuit, and a control circuit, allowing for ring oscillation by feeding back the output signal or its inverted version, enabling the confirmation of desired delay generation using a single test clock signal of lower frequency, thus simplifying the test process and reducing the number of clock signals required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a DLL circuit is optimized for high-speed operation with a fixed delay line circuit, then it can achieve high-frequency performance, but it cannot perform normal operation tests when the test clock frequency is low because the required delay amount exceeds the delay line capability
Solution Approach 1:
The delay line circuit is made dynamically adjustable by introducing a delay amount setting circuit that can change the delay amount based on control signals. This allows the same delay line circuit to adapt to different test frequencies by adjusting its delay amount, resolving the contradiction between high-speed optimization and low-frequency test capability
Solution Approach 2:
The delay amount parameter of the delay line circuit is made variable through the delay amount setting circuit. By changing the delay amount parameter according to the test clock frequency, the circuit can operate normally across a wide frequency range, from high-speed operation to low-frequency testing
2Adaptability or versatility
If two lines of clock signals are used for testing with adjusted phase differences, then the DLL circuit can be tested at low frequencies, but the burden on test device accuracy and chip layout design increases significantly
Solution Approach 1:
The phase adjustment function is extracted from the test signal configuration and integrated into the delay line circuit itself. The delay line circuit now performs both delay and phase adjustment internally, eliminating the need for external phase adjustment of multiple clock signals and reducing test device complexity
Solution Approach 2:
The delay function and phase adjustment function are merged into a single delay line circuit with controllable delay amount. This consolidation allows the circuit to achieve both high-speed operation and low-frequency testing capabilities while simplifying the test configuration to require only a single clock signal
Data Source
AI summary
A DLL circuit includes a first delay line circuit, a first phase comparison circuit, a control circuit, and a first selecting circuit. The first delay line circuit can change a delay amount and provide a delay to a first clock signal. The first phase comparison circuit can detect a phase difference between the first clock signal and an output signal of the first delay line circuit, and a phase difference between a test clock signal of which frequency is lower than the first clock signal and an output signal of the first delay line circuit or a signal after dividing the output signal. The control circuit controls a delay amount of the first delay line circuit according to the detection result of the first phase comparison circuit.