DLL Delay Control Circuit for Faster N-Value Lock Detection
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Solution Overview
Problem
Conventional DRAMs face challenges in maintaining synchronization between internal and external clock signals due to temperature-induced changes in clock cycle length, leading to extended locking times and potential misoperations.
Innovation Solution
A delay control circuit comprising an N-value detection circuit, a DLL control circuit, and a delay line circuit, which performs a pre-N-value detection operation to predict the likelihood of extended locking times and adjusts the delay operation mode between fast and normal modes to prevent misoperation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit performs a delay operation to synchronize clock signals, then the phase synchronization between internal and external clock signals is improved, but the locking time is extended beyond the scheduled execution time
Solution Approach 1:
The N-value detection circuit performs a pre-detection operation before the DLL delay operation to predict the required delay amount. By detecting the N-value (number of clock cycles) in advance, the system can prepare the appropriate delay setting beforehand, preventing extension beyond the scheduled execution time while ensuring proper phase synchronization is achieved.
Solution Approach 2:
The system uses feedback from the N-value detection circuit to dynamically adjust the DLL control. The detected N-value provides real-time information about the clock cycle relationship, allowing the DLL circuit to adjust its delay operation accordingly. This feedback mechanism ensures the locking time remains within the scheduled execution time while maintaining synchronization reliability.
2Adaptability or versatility
If the locking time is extended due to temperature-induced clock cycle changes, then the phase synchronization can be maintained under varying conditions, but the overall execution time exceeds the scheduled time
Solution Approach 1:
The system dynamically adjusts the delay operation based on detected N-values that reflect temperature-induced clock cycle changes. Rather than using a fixed delay setting, the DLL circuit adapts its delay amount according to real-time conditions, allowing it to maintain phase synchronization under varying temperatures while controlling the execution time within scheduled limits.
3Productivity
If the N-value detection sequence is performed without pre-detection, then the delay operation can proceed with default settings, but the detection sequence may exceed a specific period causing misoperation
Solution Approach 1:
The N-value detection circuit performs a pre-detection operation before the main DLL delay operation to determine the appropriate N-value in advance. This preliminary detection ensures that the subsequent delay operation uses the correct number of clock cycles, preventing the detection sequence from exceeding the specific period and avoiding misoperation while maintaining efficient detection speed.
Data Source
AI summary
Provided is a delay control circuit that can prevent an N-value detection sequence performed by the delay control circuit from exceeding a specific period. The delay control circuit includes: a DLL control circuit that sets a delay amount; a delay line circuit that performs a delay operation; and an N-value detection circuit that receives an input clock signal and an output clock signal and is configured to perform a pre-N-value detection operation. The pre-N-value detection operation includes detecting the number of delayed clock cycles from the input clock signal to the output clock signal as the number of pre-delayed clock cycles before a delay operation is performed. In response to that the number of pre-delayed clock cycles is not greater than a specific value, the DLL control circuit changes the delay amount so that the delay line circuit performs the delay operation in a fast mode.