DLL Delay Paths for Wide-Range Phase Shift Without Distortion
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Solution Overview
Problem
Existing delay-locked loop (DLL) circuits face challenges in achieving a required phase shift over a wide frequency range, particularly for higher frequency data capture, due to limitations in the number of delay circuits, which leads to duty cycle distortion and reduced phase options, making it difficult to support features like DDR3 memory applications.
Innovation Solution
The implementation of a DLL circuit with 8 delay circuit elements in a series, each with a variable delay architecture that includes decoder-controlled variable and fixed delay blocks, allowing for rerouting of the input signal through different delay paths to achieve a wide frequency range without the need for frequency overlap across PVT corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of delay circuits is increased to achieve required phase shift over wide frequency range, then phase shift capability is improved, but duty cycle distortion increases and device complexity increases
Solution Approach 1:
The delay circuit is divided into multiple delay elements (first, second, third delay elements) that can be independently controlled. Each delay element can be selectively enabled or disabled through control signals, allowing the total delay to be segmented and adjusted in steps. This segmentation enables achieving required phase shifts without needing a large number of continuously connected delay circuits, thereby reducing duty cycle distortion and device complexity.
2Speed
If the number of delay circuits is increased to support higher frequency data capture, then frequency range is improved, but duty cycle distortion increases
Solution Approach 1:
The delay circuit employs dynamic control mechanisms where control signals selectively enable or disable specific delay elements based on the required frequency range and phase shift. This dynamic adjustment allows the circuit to adapt to different frequencies without constantly operating at maximum complexity, thereby maintaining signal integrity and reducing duty cycle distortion while supporting higher frequency data capture.
3Manufacturing precision
If delay circuits are configured with fixed delay blocks, then manufacturing precision is improved, but adaptability to different frequencies is reduced
Solution Approach 1:
The delay circuit is segmented into multiple delay elements with fixed delay blocks within each element. Each delay element can be independently controlled through control signals, allowing the circuit to achieve variable total delay by selectively enabling or disabling segments. This segmentation maintains the manufacturing precision of fixed delay blocks while providing adaptability to different frequencies through combinatorial control of the segmented elements.
Solution Approach 2:
The delay circuit is designed with universal control mechanisms that can selectively activate different combinations of delay elements to achieve various delay values. The control logic universally manages multiple delay elements, allowing the same hardware configuration to serve multiple frequency ranges and phase shift requirements, thereby achieving both manufacturing precision and frequency adaptability.
Data Source
AI summary
A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.