DLL Delay Control Using Pre-N Detection for Faster Clock Locking
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Solution Overview
Problem
Conventional DRAMs face extended locking times in delay-locked loop circuits due to variations in clock cycle length, leading to potential misoperations when the locking time exceeds scheduled execution times.
Innovation Solution
A delay control method that includes a pre-N-value detection operation to predict potential extensions in locking time, adjusting the delay amount by increasing the variation rate to prevent the N-value detection sequence from exceeding a specific period, allowing for fast or normal mode operations based on the detected pre-N-value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay operation is performed with a fixed delay amount, then the DLL circuit can maintain stable operation, but the locking time is extended when the clock cycle is longer than the existing delay time, causing the N-value detection sequence to exceed the scheduled execution time
Solution Approach 1:
The delay amount is made dynamic rather than fixed. The DLL control circuit adjusts the delay amount in multiple stages: initially setting it to a first value, then changing to a second value when the phase difference becomes smaller than a reference value, and finally setting to a third value when synchronization is achieved. This dynamic adjustment allows the system to adapt to different clock cycle lengths and prevent the N-value detection sequence from exceeding the scheduled execution time.
Solution Approach 2:
The invention changes the delay amount parameter based on the phase difference between the internal clock signal and external clock signal. By monitoring the phase difference and adjusting the delay amount accordingly (first value → second value → third value), the system optimizes the locking time while maintaining stable operation. This parameter change strategy directly addresses the contradiction between stability and locking time.
2Loss of time
If the delay amount is increased to reduce locking time, then the N-value detection sequence can complete within the scheduled execution time, but the phase synchronization accuracy may be compromised
Solution Approach 1:
The delay amount is dynamically adjusted in three stages based on phase difference measurements. Initially, a first delay value is applied to establish rough synchronization. When the phase difference becomes smaller than a reference value, the delay amount changes to a second value for finer adjustment. Finally, when synchronization is achieved, a third value is set. This multi-stage dynamic approach ensures both reduced locking time and maintained phase synchronization accuracy.
Solution Approach 2:
The DLL control circuit performs periodic phase difference detection and delay amount adjustment. The system continuously monitors the phase difference between internal and external clock signals and adjusts the delay amount in periodic cycles. This periodic action allows the system to achieve fast initial locking while maintaining accurate phase synchronization through continuous refinement.
Data Source
AI summary
A delay control method includes the following steps. A pre-N-value detection operation is performed comprising detecting a number of delayed clock cycles from an input clock signal to an output clock signal as a number of pre-delayed clock cycles before a delay operation is performed. A delay amount is set by a DLL control circuit according to a phase difference between the input clock signal and the output clock signal and the number of pre-delayed clock cycles. A control signal representing the delay amount is output by the DLL control circuit. The delay operation is performed by a delay line circuit according to the control signal, wherein the delay operation comprises delaying the input clock signal based on the delay amount and generating the output clock signal so that the input clock signal and the output clock signal are synchronous.