Delay-Locked Loop Clock Delay Selection for Stable Data Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay locked loops (DLLs) in synchronous semiconductor memory devices face challenges in maintaining a sufficient data margin, especially at high-frequency clocks, and are sensitive to changes in external power supply voltage, making accurate operation state estimation difficult and requiring additional data strobe signals.
Innovation Solution
The proposed DLL includes a selection block that generates a selection signal during the DLL-OFF MODE to selectively determine the delay time of the internal clock, and an auxiliary delay block that compensates for voltage-level changes, allowing for improved data margin and stability even when the DLL is off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the DLL is turned off to reduce power consumption, then current dissipation is reduced, but data margin becomes insufficient and operation state estimation becomes difficult
Solution Approach 1:
The delay time of the internal clock is made dynamically adjustable through the selection block, which can select from multiple preset delay values. This dynamic adjustment capability allows the system to optimize performance for different operating conditions, enabling sufficient data margin even when the DLL is turned off for power savings.
Solution Approach 2:
The invention changes the delay time parameter of the internal clock by introducing a selection block that can choose from multiple preset delay values. This parameter adjustment compensates for the insufficient data margin that would normally occur when the DLL is turned off, allowing the system to maintain reliability while reducing power consumption.
2Device complexity
If the delay time is fixed to simplify the circuit, then device complexity is reduced, but the system becomes sensitive to power supply voltage changes and cannot maintain sufficient data margin
Solution Approach 1:
The delay control function is segmented into multiple fixed delay stages, each providing a predetermined delay value. The selection block can choose from these segmented delay options, allowing the system to maintain simplicity while achieving variable delay capability to compensate for voltage variations and ensure sufficient data margin.
3Productivity
If the DLL operates at high-frequency clock to improve productivity, then data transmission speed is increased, but data margin becomes insufficient and additional data strobe signals are required
Solution Approach 1:
The selection block enables dynamic adjustment of the internal clock delay time, allowing the system to optimize the phase relationship between clocks at high frequencies. This dynamic control compensates for the reduced data margin that occurs at high frequencies, eliminating the need for additional data strobe signals while maintaining high productivity.
Data Source
AI summary
A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.