DLL Delay Circuit Layout for Clock Skew and Jitter Reduction
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Solution Overview
Problem
Semiconductor devices face synchronization challenges due to internal time delays when using externally applied clocks, leading to clock skew, which existing delay-locked loop (DLL) circuits struggle to effectively compensate for.
Innovation Solution
A DLL circuit with a phase splitter, logic gate, and cascade-connected delay cells that split and delay reference clock signals based on control codes to generate synchronized clock signals, adjusting delay amounts to minimize clock skew and reduce bang-bang jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing DLL circuits are used to compensate for internal time delays, then clock skew can be reduced, but synchronization accuracy and stability deteriorate due to bang-bang jitter
Solution Approach 1:
The delay line is divided into multiple delay units, each contributing a fixed delay amount. By segmenting the total delay into discrete units and using multiple parallel paths with different numbers of delay units, the circuit achieves fine-grained delay control. This segmentation allows precise matching of clock phases without the coarse quantization that causes bang-bang jitter in traditional DLLs.
Solution Approach 2:
The invention introduces a new dimension of delay control by varying the number of delay units in parallel paths rather than just adjusting the delay amount in a single path. This dimensional change from continuous delay adjustment to discrete path selection enables precise delay matching while maintaining circuit stability and reducing jitter.
2Reliability
If delay amount is increased to compensate for internal time delays, then clock skew is reduced, but delay precision deteriorates
Solution Approach 1:
The total delay compensation is segmented into multiple fixed delay units arranged in parallel paths. Each delay unit provides a precise, fixed delay amount, and by selecting different combinations of these units in parallel, the circuit achieves fine-grained delay adjustment. This segmentation transforms a continuous delay adjustment problem into a discrete selection problem, improving both precision and controllability.
Solution Approach 2:
The delay configuration is made dynamic and adjustable through control signals that select which parallel paths are activated. This dynamic reconfiguration allows the delay precision to be optimized for different operating conditions and clock frequencies, rather than being fixed for a single operating point.
3Reliability
If traditional delay line configuration is used, then circuit simplicity is maintained, but delay resolution and synchronization stability deteriorate
Solution Approach 1:
The delay line is segmented into multiple identical delay units that can be replicated and arranged in parallel. This modular segmentation improves delay resolution and synchronization stability while keeping each individual unit simple and standardized, making the overall design manageable despite the increased number of components.
Solution Approach 2:
The parallel path delay units are designed to be universal and identical in structure, each capable of providing the same delay function. This universality simplifies design and verification while achieving improved performance through the collective arrangement of multiple units. The same delay unit design can be reused across different paths with different configurations.
Data Source
AI summary
A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.