Register-Controlled DLL Delay Staging for High-Frequency Jitter Reduction
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Solution Overview
Problem
Conventional register controlled DLL circuits face difficulties in finely adjusting delay durations when operating at high frequencies, leading to increased jitter in clock signals due to limited variability in adjustable delay durations.
Innovation Solution
The proposed register controlled DLL circuit employs a clock delay circuit that uses first and second delay units with different durations, allowing for adjustable delay settings based on operation frequency, enabling finer adjustments and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional register controlled DLL circuit uses fixed delay units, then the circuit structure is simple, but the adjustable delay duration has limited variability at high frequencies leading to increased jitter
Solution Approach 1:
The clock delay circuit is segmented into multiple delay units (first delay units and second delay units) with different delay durations. Each delay unit can be independently selected and activated based on the operation frequency, allowing fine-grained adjustment of the total delay duration. This segmentation enables precise delay control at high frequencies by combining different delay units in series.
Solution Approach 2:
The delay units are configured to be dynamically selectable based on operation frequency. A frequency detection circuit identifies the current frequency range and activates the appropriate combination of delay units. This dynamic configuration allows the system to adapt the delay duration to match the operation frequency, achieving fine adjustment precision at high frequencies while maintaining circuit simplicity through automated selection.
2Adaptability or versatility
If the DLL circuit uses a single type of delay unit, then the circuit design is straightforward, but the delay duration cannot be finely adjusted at high operation frequencies
Solution Approach 1:
Different delay units are assigned different delay durations (first delay units with shorter duration, second delay units with longer duration) to match different frequency ranges. The frequency detection circuit locally activates the appropriate delay units based on the current operation frequency, providing locally optimized delay adjustment for each frequency range rather than using a uniform delay unit throughout.
Solution Approach 2:
The clock delay circuit achieves multi-functionality by incorporating both first and second delay units that can be activated in different combinations. This universal design allows the same circuit structure to handle a wide range of frequencies from low to high, with each delay unit type serving multiple frequency ranges when combined with others, thereby improving adaptability without proportionally increasing complexity.
3Reliability
If the delay duration is fixed, then the circuit operation is stable, but the internal clock cannot be synchronized with external clock at varying frequencies
Solution Approach 1:
A frequency detection circuit continuously monitors the operation frequency and provides feedback to the delay units control circuit. Based on this feedback, the control circuit dynamically adjusts which delay units are activated to achieve the appropriate delay duration for the current frequency. This closed-loop feedback mechanism ensures reliable clock synchronization across varying frequencies while maintaining system stability through automated adjustment.
Solution Approach 2:
The delay units are pre-configured with different delay durations and organized in a selectable arrangement before operation. The frequency detection circuit identifies the current frequency range in advance and activates the pre-configured appropriate delay units before the clock synchronization process begins. This preliminary configuration ensures that the correct delay settings are ready when needed, enabling stable synchronization across different frequencies without real-time calculation delays.
Data Source
AI summary
A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit configured to delay a phase of an internal clock synchronized with a clock edge of the source clock in response to an output signal of the phase comparator. The clock delay circuit delays the phase of the internal clock using first delay units for a predetermined delay duration, and thereafter delays the phase of the internal clock using second delay units, the second delay unit providing a longer delay than the first delay unit. A delay replica model is configured to reflect actual delay conditions of the source clock in an output clock of the clock delay circuit to output the feedback clock.