Duty Cycle Correction in DLLs for Delay Variation Tracking
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Solution Overview
Problem
Conventional DLL circuits fail to adequately reflect variations in internal delay elements caused by external factors like power-supply voltage changes, leading to increased data access time and faulty operations in high-frequency synchronous memory devices.
Innovation Solution
A Duty Cycle Correction (DCC) circuit that generates internal clock signals by mixing phases of first and second clock input signals, using a clock input unit with delays and multiplexers to ensure proper reflection of internal delay element variations, even during abrupt power-supply voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the second DLL is switched off to reduce current consumption, then current consumption is reduced, but the internal delay element variation is not reflected in the generated clock signal
Solution Approach 1:
The patent stores the first clock input signal (clk_r) in a storage element before the second DLL is switched off. This preliminary action ensures that when the second DLL needs to recover from a power-supply voltage change, the stored signal provides the necessary reference to quickly re-establish the locking state without requiring the second DLL to remain continuously active, thus maintaining reliability while reducing current consumption.
2Use of energy by moving object
If the DLL circuit uses a single clock input signal after locking, then current consumption is reduced, but the system cannot adapt to power-supply voltage changes
Solution Approach 1:
The patent employs a phase detector that continuously monitors the phase relationship between the first and second feedback clock signals. When a power-supply voltage change causes phase deviation, the phase detector generates a control signal that adjusts the delay elements to restore proper phase alignment. This feedback mechanism enables the system to adapt to power-supply variations while maintaining low current consumption by keeping the second DLL in a low-power state.
Solution Approach 2:
The stored first clock input signal serves the dual purpose of being the current operating signal and providing the reference needed for rapid recovery when disturbances occur. This self-service approach eliminates the need for separate reference signals or continuous operation of both DLLs, allowing the system to adapt to changes while maintaining energy efficiency.
3Use of energy by moving object
If the second DLL remains in OFF state, then current consumption is minimized, but data access time increases due to insufficient delay element reflection
Solution Approach 1:
The patent stores the first clock input signal in advance, creating a ready reference that enables rapid recovery of the second DLL when needed. This preliminary preparation ensures that when power-supply voltage changes occur, the second DLL can quickly re-synchronize without causing significant data access time penalties, thus balancing low current consumption with acceptable timing performance.
Data Source
AI summary
A duty cycle correction (DCC) circuit and a delayed locked loop (DLL) circuit using the same are disclosed. The DCC circuit is operated by an enable signal which is enabled when the DLL is locked. The duty cycle correction (DCC) circuit includes a clock input unit and a duty cycle mixing unit. The clock input unit receives the enable signal and first and second clock input signals having opposite phases, generates an inverting signal of the first clock input signal, and when the enable signal is enabled, generates first and second internal clock signals, based on the first and second clock input signals and the inverting signal. The duty cycle mixing unit mixes a phase of the first internal clock signal with a phase of the second internal clock signal.