Type I DLL Deskew Circuit for Jitter Peaking Suppression
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Solution Overview
Problem
Type I Delay-Locked Loops (DLLs) face challenges in suppressing jitter, which leads to timing errors in output signals due to noise amplification and the inability to distinguish between input and output jitter, resulting in jitter peaking.
Innovation Solution
Incorporating a deskew element that synchronizes transitions between input and output signals, ensuring the output signal changes state only when both are in the same state, effectively suppressing jitter by adjusting the delay line length to match the phase of the input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Type I DLL is used to generate a phase-matched output signal, then the output signal is locked to the input signal phase, but jitter accumulates and amplifies through the delay line causing timing errors
Solution Approach 1:
A deskew element is introduced as an intermediary component between the delay line output and the final output. This deskew element receives both the input signal and the delayed output signal, compares their transitions, and only passes output transitions that are synchronized with input transitions, thereby filtering out jitter while preserving the phase-locked signal
Solution Approach 2:
The phase detector continuously compares the input signal with the delayed output signal and generates a feedback control signal that adjusts the delay line to maintain phase locking. The deskew element adds another layer of feedback by monitoring transition synchronization and suppressing output transitions that do not align with input transitions, creating a dual-feedback mechanism for jitter suppression
Data Source
AI summary
In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.