DLL Clock Divider Synchronization to Prevent Memory Latency
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Solution Overview
Problem
Conventional DLL circuits often cause internal clocks to become either fully pulsed ahead or behind external clocks due to clock skew compensation, leading to latency issues in semiconductor memory devices, especially at lower operating voltages and noise frequencies.
Innovation Solution
A DLL circuit design that includes a first divider for the external clock, a second divider for the internal clock, a phase detector to measure phase differences, and an adjusting unit to synchronize the internal clock with the external clock, using a value M to determine the division ratio and adjust the internal clock accordingly, thereby preventing latency problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional DLL circuit is used to compensate for clock skew, then the internal clock phase is adjusted to match the external clock, but the internal clock may become a full pulse ahead or behind the external clock causing latency issues
Solution Approach 1:
The patent segments the clock signal processing into multiple divided versions (first divided signal from external clock, second divided signal from internal clock). By dividing the clocks into multiple phases and comparing them separately, the system can detect phase differences more precisely without causing full-pulse latency shifts that occur in conventional single-path DLL circuits.
Solution Approach 2:
The patent introduces divided clock signals as intermediary representations between the external and internal clocks. Instead of directly comparing original clock signals, the phase detector compares divided versions, which allows for finer phase adjustment and prevents the internal clock from shifting by full pulse periods, thereby reducing latency while maintaining synchronization accuracy.
2Measurement precision
If the division ratio M is increased to improve phase detection precision, then the synchronization accuracy improves, but the circuit complexity increases
Solution Approach 1:
The patent employs dynamic division ratios (different M values for first and second dividers) that can be adjusted based on operating conditions. The first divider uses division value M1 and the second divider uses division value M2, allowing the system to optimize phase detection precision dynamically while managing circuit complexity through selective division ratios rather than uniformly high division across all paths.
Solution Approach 2:
The patent changes the division parameters (M1 and M2) to achieve optimal phase detection precision. By selecting appropriate division values for each clock path, the system can enhance measurement precision without requiring excessively high division ratios throughout the entire circuit, thus balancing precision requirements with circuit complexity constraints.
Data Source
AI summary
A delay locked loop (DLL) circuit having improved noise characteristics. The DLL circuit includes a first divider for generating a first divided signal by dividing an external clock; a second divider for generating a second divided signal by dividing an internal clock; a phase detector for detecting a phase difference between the first divided signal and the second divided signal; and an adjusting unit for synchronizing the internal clock and the external clock, based on the phase difference.