DLL Driver Clock Gating for Lower Memory Current Consumption
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Solution Overview
Problem
Conventional DLL circuits in semiconductor memory devices consume excessive current due to unnecessary clock toggling during active modes, even when clocks are not needed, leading to high power consumption.
Innovation Solution
A DLL driver control circuit that includes a counter to count DLL clocks, a comparator to compare the counted value with a setting value, and an SR latch to generate a control signal that only enables the DLL driver during active mode intervals when data operations occur, preventing meaningless toggling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL driver is always enabled during active mode, then clock synchronization is maintained, but current consumption increases due to unnecessary clock toggling
Solution Approach 1:
The DLL driver controller dynamically adjusts the enable state of the DLL driver based on real-time detection of clock necessity. The system transitions between enabled and disabled states according to whether clock signals are actually needed, making the system adaptable rather than static. This resolves the contradiction by allowing the system to maintain reliability when clocks are needed while reducing energy consumption when they are not.
Solution Approach 2:
The system implements a feedback mechanism where the DLL driver controller continuously monitors whether clock signals are required and adjusts the DLL driver enable state accordingly. The controller receives feedback about the operational state (whether read/write operations are occurring) and uses this information to control the DLL driver, creating a closed-loop system that optimizes both reliability and energy efficiency.
2Use of energy by moving object
If the DLL driver is turned off to reduce power consumption, then current consumption decreases, but clock synchronization may be compromised
Solution Approach 1:
The system dynamically switches between powered-off and powered-on states based on actual operational needs. Rather than maintaining a fixed state, the DLL driver controller adjusts the enable signal in real-time, allowing the system to achieve low power consumption during idle periods while ensuring clock synchronization is maintained when data operations require it.
Solution Approach 2:
The feedback mechanism ensures that the DLL driver is only turned off when clock signals are genuinely unnecessary. The controller monitors operational conditions and provides feedback to the enable logic, preventing premature shutdown that would compromise synchronization while avoiding unnecessary operation that would waste energy.
3Manufacturing precision
If DLL clocks are toggled frequently to maintain synchronization, then timing accuracy is improved, but energy wastage increases
Solution Approach 1:
Instead of continuous clock toggling, the system implements periodic action by only enabling clock signals during specific intervals when data operations are detected. The DLL driver controller activates the DLL driver periodically based on the presence of read/write operations, rather than maintaining continuous operation. This reduces energy wastage while maintaining timing accuracy during active periods.
Solution Approach 2:
The system applies partial action by providing clock signals only for the portion of time when they are actually needed, rather than continuously. The DLL driver controller enables the driver partially - only during intervals when data operations require clock synchronization - thereby eliminating excessive action that would cause energy wastage without compromising timing accuracy during necessary periods.
Data Source
AI summary
A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.