DLL Initialization Circuit Using Dual-Edge Delay Measurement
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Solution Overview
Problem
Existing delay locked loops (DLLs) in synchronous memory devices require significant time to achieve synchronization of internal and external clock signals, with initial delay settings often resulting in unnecessary delays due to reliance on a single clock edge for measurement initialization.
Innovation Solution
The implementation of measurement initialization circuitry that allows for the use of either the rising or falling edge of a reference clock signal to generate a 'Stop' signal, reducing the time required to initialize the variable delay line and potentially saving half a clock period by enabling immediate stoppage of the 'Start' signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single clock edge is used for measurement initialization in conventional DLLs, then the circuit operation is simple, but the synchronization time is excessively long
Solution Approach 1:
The patent segments the single clock edge measurement into two separate measurements: one using the rising edge and another using the falling edge. This segmentation allows the system to capture propagation delays more efficiently by utilizing both edges of the clock signal, thereby reducing the overall synchronization time without significantly increasing circuit complexity.
Solution Approach 2:
The patent performs preliminary measurements of propagation delay using both rising and falling edges before the actual synchronization process. By pre-characterizing the delay characteristics of the delay line stages during initialization, the system can faster achieve lock condition during normal operation, reducing the synchronization time.
2Use of energy by moving object
If the variable delay line is initialized with minimal delay, then power consumption is reduced, but the lock condition cannot be achieved quickly
Solution Approach 1:
The patent performs preliminary measurement of the actual propagation delay through the delay line using both clock edges during an initialization phase. Based on these measurements, the system determines the appropriate number of stages and initial delay setting needed to achieve lock condition. This preliminary characterization allows the system to start from a more accurate initial state, reducing both power consumption and lock time.
Solution Approach 2:
The patent dynamically adjusts the delay parameters of the variable delay line based on measured propagation delays from both rising and falling edges. By changing the delay parameters according to actual circuit characteristics rather than using fixed minimal delay, the system optimizes the balance between power consumption and lock acquisition speed.
3Productivity
If measurement initialization uses both rising and falling edges, then synchronization speed is improved, but the circuit complexity increases
Solution Approach 1:
The patent designs the measurement initialization circuit to serve multiple functions: it measures propagation delay using both rising and falling edges, determines the optimal number of delay stages, and initializes the variable delay line settings. By making the measurement circuit multi-functional, the patent achieves faster synchronization without proportionally increasing circuit complexity, as the same circuit infrastructure is used for multiple measurement and initialization tasks.
Data Source
AI summary
Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.