DLL Measurement Initialization Using Dual-Edge Stop Signals
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Solution Overview
Problem
Existing delay locked loop (DLL) circuits in synchronous memory devices require significant time to achieve synchronization due to the initial delay setting method, which can be inefficient and consume more power, especially when only the rising edge of the clock signal is used to generate the 'Stop' signal.
Innovation Solution
The implementation of measurement initialization circuitry that allows either the rising or falling edge of a reference clock signal to generate a 'Stop' signal, reducing the time required to initialize the variable delay line and potentially saving half a clock period by using both edges for synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If only the rising edge of the clock signal is used to generate the 'Stop' signal in DLL circuits, then the circuit design is simpler, but the time required to initialize the variable delay line increases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-charging all latches in the variable delay line to a known state (logic 0) before the measurement process begins. This preliminary initialization ensures that when the measurement clock signal is applied, the latches are ready to immediately capture and propagate the signal without additional delay, thereby reducing the overall initialization time while maintaining circuit simplicity
Solution Approach 2:
The patent employs periodic action by using both the rising and falling edges of the clock signal to generate measurement clock signals. Instead of relying on a single edge, the circuit alternates between rising and falling edges to create multiple measurement opportunities within each clock cycle, effectively halving the initialization time while adding minimal complexity through edge detection logic
2Productivity
If both rising and falling edges of the clock signal are used to generate 'Stop' signals, then the synchronization time is reduced by half a clock period, but the circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the clock signal processing into separate paths for rising edge detection and falling edge detection. Each edge type is handled by dedicated circuitry that generates its own measurement clock signal, allowing parallel processing of both edges without interference. This segmented approach enables faster synchronization while keeping each individual circuit segment relatively simple
Solution Approach 2:
The patent uses an intermediary measurement clock signal that is derived from both rising and falling edges of the reference clock. This intermediate signal serves as a bridge between the reference clock and the latches, allowing the system to utilize both clock edges without directly complicating the main clock distribution network. The measurement clock acts as a mediator that simplifies the overall circuit architecture while achieving the desired dual-edge functionality
3Measurement precision
If the variable delay line is initialized with a longer measurement period, then the delay measurement is more accurate, but the power consumption during initialization increases
Solution Approach 1:
The patent employs periodic action by utilizing both rising and falling edges of the clock signal within a single measurement period. This creates two measurement opportunities (one per edge) without extending the overall measurement duration, thereby maintaining measurement accuracy while halving the time-related power consumption during initialization
Solution Approach 2:
The patent ensures continuity of useful action by keeping the latches in a constant ready state through pre-charging, and by continuously monitoring both rising and falling edges without idle periods. This eliminates gaps in the measurement process where power would be consumed without productive measurement, thereby improving the ratio of useful measurement to power consumption while maintaining accuracy
Data Source
AI summary
Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.