Delay-Locked Loop Duty Correction for Stable High-Frequency Clocks
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Solution Overview
Problem
DLL circuits face challenges in maintaining a constant duty ratio of the output clock signal due to duty skew in external clock signals, which worsens with increasing frequency, leading to potential malfunctioning of electronic systems like semiconductor memory devices.
Innovation Solution
A delay-locked loop with a duty correction block that performs first and second duty correction operations to maintain a constant duty ratio, using a cascade of delay cells and control signals to correct the duty ratio of both input and output clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating frequency of the DLL circuit is increased, then the productivity of the electronic system is improved, but the duty ratio distortion of the output clock signal becomes more serious
Solution Approach 1:
The patent applies preliminary action by performing duty ratio correction on the input clock signal before it enters the delay line. The first duty correction block corrects the duty ratio of the input clock signal in advance, preventing duty skew accumulation during subsequent delay operations. This proactive correction ensures that even at high operating frequencies, the duty ratio remains stable and does not deteriorate with increased frequency.
2Device complexity
If a simple delay line structure is used, then the device complexity is reduced, but the ability to maintain constant duty ratio deteriorates
Solution Approach 1:
The patent segments the duty correction function into two distinct blocks: a first duty correction block for correcting the input clock signal before the delay line, and a second duty correction block for correcting the output clock signal after the delay line. This segmentation allows each block to perform a specific correction function, maintaining constant duty ratio through a modular and manageable circuit structure rather than requiring a completely complex redesign.
Solution Approach 2:
The patent implements feedback mechanisms where duty correction blocks receive feedback signals indicating the duty ratio status of clock signals. The duty correction control block adjusts control signals based on this feedback to maintain the duty ratio at a target value (e.g., 50%). This closed-loop feedback control enables the circuit to automatically compensate for duty skew without requiring overly complex open-loop structures.
Data Source
AI summary
A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected.