Delay-Locked Loop Circuit Duty Cycle Distortion Control
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Solution Overview
Problem
DLL circuits are sensitive to additional delays, leading to duty cycle distortion and potential false locking and harmonic locking issues, which affect the quality of output clocks and require complex design techniques to mitigate.
Innovation Solution
A DLL circuit design that includes a variable delay line with adjustable stages, a phase comparator, and a delay control signal generator to match the total delay to the reference signal period, along with start-up control circuitry to minimize initial delay and prevent false locking, effectively isolating input path delays from the feedback loop and allowing for a wide range of delay variations without pre-setting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional delays are introduced in the DLL circuit, then the circuit can accommodate wider delay variations, but duty cycle distortion increases and output quality deteriorates
Solution Approach 1:
The delay line is divided into multiple identical stages, each contributing a controlled portion of the total delay. This segmentation allows the total delay to be adjusted across a wide range while maintaining uniform delay distribution, thereby preventing duty cycle distortion even when accommodating wide delay variations.
Solution Approach 2:
The circuit changes the delay parameter of each stage in response to detected duty cycle distortion. By dynamically adjusting the delay parameter based on feedback about distortion levels, the circuit can accommodate varying delay conditions while actively correcting to maintain high output quality and prevent distortion accumulation.
2Reliability
If complex design techniques are used to mitigate false locking and harmonic locking, then reliability improves, but device complexity increases
Solution Approach 1:
A feedback mechanism detects duty cycle distortion and generates corrections to prevent false locking and harmonic locking. This feedback-based approach improves reliability by actively monitoring and correcting locking conditions, while avoiding the need for complex pre-configured mitigation techniques, thus maintaining relatively simple circuit structure.
Solution Approach 2:
The circuit performs preliminary delay adjustment to optimize the delay value before the locking process begins. By pre-configuring the delay line with an optimized delay value that accounts for expected variations, the circuit prevents false locking and harmonic locking from occurring in the first place, thereby improving reliability without requiring complex real-time correction mechanisms.
Data Source
AI summary
A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within the delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages.