DLL Duty Cycle Correction With Independent Edge Control
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits fail to correct the duty cycle, limiting the maximum frequency and speed of operation in high-speed circuits that use double data rate, where both rising and falling edges trigger data operations.
Innovation Solution
A DLL circuit with a duty cycle correction (DCC) loop that controls the falling edge to achieve a 50% duty cycle, using a shared delay line with independent controls for rising and falling edges, reducing circuit size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DLL circuits are used to generate clock signals, then the circuit structure is simple, but the duty cycle cannot be corrected which limits the maximum frequency and speed of operation
Solution Approach 1:
The patent segments the clock signal processing into two independent paths: one for rising edge control and one for falling edge control. By dividing the duty cycle correction function into separate rising edge correction and falling edge correction circuits, each operating independently on their respective edges, the system achieves precise duty cycle control without requiring a complete redesign of the entire DLL circuit, thus improving speed while managing complexity.
Solution Approach 2:
The patent merges the duty cycle correction function with the existing DLL circuit by integrating correction circuits into the delay line structure. The rising edge correction circuit and falling edge correction circuit are combined with the main DLL delay elements, allowing duty cycle correction to be achieved within the existing circuit framework rather than as a separate system, thereby improving performance without proportionally increasing overall complexity.
2Manufacturing precision
If duty cycle correction is implemented by controlling both rising and falling edges independently, then accurate duty cycle correction is achieved, but the circuit complexity increases
Solution Approach 1:
The patent applies local quality by implementing separate correction circuits that operate locally on specific edges: the rising edge correction circuit processes only rising edges, and the falling edge correction circuit processes only falling edges. Each circuit is optimized for its specific function with dedicated delay elements and control logic, achieving high duty cycle accuracy for each edge independently while keeping each local circuit relatively simple rather than creating one complex universal circuit.
Solution Approach 2:
The delay line structure serves multiple functions: it provides the main clock signal delay for the DLL operation and simultaneously serves as the correction medium for both rising and falling edge duty cycle correction. The same delay line infrastructure is utilized by both correction circuits, allowing the system to achieve precise duty cycle control through independent control voltages applied to the shared delay elements, thereby reducing overall circuit complexity.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a delay line which receives an input clock, and provides an output clock which is phase shifted 360 degrees and an intermediate clock which is phase shifted less than 360 degrees from the input clock. A DLL loop receives the input clock as a DLL reference clock and the output clock as a DLL feedback clock, and outputs a first control voltage to adjust first edges of the input clock. A duty cycle correction (DCC) loop receives the intermediate clock as a DCC reference clock and an inverse of the output clock as a DCC feedback clock, and outputs a second control voltage to adjust second edges of the input clock, independent of the first edges of the input clock. The DCC loop is enabled after the DLL loop achieves lock between the first edges of the output clock and the input clock.